State Confidence Error Correction Module for NAND Flash
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Solution Overview
Problem
As memory cell sizes in NAND flash devices decrease, the raw bit error rate increases, and existing error correction codes like BCH may not provide sufficient error correction capability, necessitating improved techniques for generating state confidence data to enhance error correction efficiency.
Innovation Solution
The implementation of a system that includes a state confidence error correction module to manage and encode state confidence data, using multiple sense operations and encoding schemes to accurately determine the logical state of memory cells, enabling more robust error correction through LDPC error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is decreased to increase storage density, then storage capacity is improved, but raw bit error rate increases
Solution Approach 1:
The patent applies parameter changes by transitioning from BCH code to LDPC code, fundamentally changing the error correction parameters and algorithms. This allows the system to maintain effective error correction capability as memory cell size decreases and storage density increases, thereby addressing the contradiction between higher storage capacity and higher bit error rate
2Reliability
If BCH error correction code is used, then error correction capability is provided, but correction capability is insufficient for future generation NAND products
Solution Approach 1:
The patent changes the error correction code parameter from BCH to LDPC, providing a more adaptable and powerful correction capability that can handle the increased error rates in future generation NAND products with smaller memory cells
3Reliability
If LDPC error correction code is used, then error correction capability is improved, but state confidence data must be provided in a different manner
Solution Approach 1:
The patent introduces state confidence data as an intermediary element that bridges the memory read operation and LDPC error correction. This intermediary contains reliability information about each bit, allowing the LDPC decoder to make more informed correction decisions while managing the added complexity through structured data handling
Data Source
AI summary
An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.