Interleaver Address Generation Circuit for Flexible Window Configurations
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Solution Overview
Problem
Conventional interleaver circuits face inefficiencies and increased Bit Error Rate (BER) performance issues when generating next interleaver addresses, particularly at high data rates, due to limitations in determining window sizes and requiring additional circuitry for parallel decoders, which can be impractical in integrated circuits like programmable logic devices.
Innovation Solution
A method and circuit for generating interleaver addresses by dividing data blocks into m windows of N/m bits, calculating interleaver addresses as a function of modulo N/m, and generating window select values based on modulo m, allowing for flexible window sizes and reducing the need for additional address generators and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interleaver circuits use most significant bits of interleaver address as window select signals in parallel decoders, then data throughput is improved, but the number of windows must be powers of two and additional circuitry is required
Solution Approach 1:
The patent changes the parameter used for window selection from most significant bits to least significant bits of the interleaver address. This allows the number of windows to be any integer value rather than restricted to powers of two, while still enabling parallel decoder operation for increased throughput. The invention modifies the addressing scheme parameter to achieve flexibility in window configuration.
Solution Approach 2:
The patent inverts the conventional approach by using the least significant bits instead of the most significant bits for window selection. This inversion allows the window select signal to be derived from the same address generator without requiring additional circuitry, while still enabling parallel processing. The inverted bit selection resolves the contradiction between throughput and complexity.
2Productivity
If separate address generators are used for each MAP decoder in parallel, then decoding throughput is improved, but BER performance deteriorates when the last window length is small
Solution Approach 1:
The patent makes a single address generator serve multiple MAP decoders by using the least significant bits for window selection. This universal address generator produces addresses that are properly distributed across all windows, including the last window with potentially small length, thereby maintaining BER performance while still enabling parallel decoding for improved throughput.
3Ease of operation
If BRAM look up table is used to generate interleaver addresses and window select signals, then address generation is simplified, but memory requirements make it impractical for certain integrated circuits
Solution Approach 1:
The patent replaces the mechanical/memory-based BRAM look up table system with a computational arithmetic system. Instead of storing pre-computed addresses in memory, the invention uses arithmetic operations (modulo arithmetic) on the interleaver address to generate both the address and window select signal dynamically. This substitution eliminates large memory requirements while maintaining the simplicity of address generation through systematic computation.
Data Source
AI summary
A method of generating interleaver addresses in a circuit for decoding data is disclosed. The method comprises the steps of receiving a data stream having a plurality of data blocks, each block having N bits; dividing each data block of the plurality of data blocks into m windows, each window comprising N/m bits; and calculating an interleaver address for each window as a function of modulo N/m. A circuit for generating an interleaver address in a circuit for decoding data is also disclosed.