Adaptive Booster Scheme for Memory Arrays
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Solution Overview
Problem
Existing memory technologies face challenges in providing uniform and efficient voltage boosting across memory arrays, particularly in flash memory systems, leading to inconsistencies in read access speed and reliability due to varying distances from voltage sources.
Innovation Solution
The implementation of a boost converter circuitry with multiple DC-to-DC converters and a switch mechanism that dynamically couples or decouples boost converters based on the distance of memory arrays from the converters, ensuring consistent voltage ramp rates and levels across all arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage source is used for all memory arrays, then device complexity is reduced, but voltage uniformity and read access reliability deteriorate due to varying distances from the voltage source
Solution Approach 1:
The voltage boosting system is segmented into multiple independent boost converter circuits, each serving a specific memory array or group of arrays. This segmentation allows each converter to provide localized voltage boosting, ensuring uniform voltage delivery regardless of distance from the voltage source, thereby resolving the contradiction between device complexity and read access reliability.
Solution Approach 2:
Each memory array is equipped with its own dedicated boost converter circuit, providing localized voltage boosting exactly where needed. This local quality approach ensures that every array receives consistent voltage ramp rates and levels independent of its position in the memory device, eliminating the reliability issues caused by distance variations while maintaining manageable system complexity.
2Reliability
If multiple boost converters are placed close to each memory array, then voltage uniformity and read access speed are improved, but die size increases
Solution Approach 1:
The boost converter circuits are designed with multi-functionality to serve multiple purposes: they provide voltage boosting for read operations, support write operations, and can be selectively activated based on which memory array is being accessed. This universality allows the system to achieve voltage uniformity across all arrays without proportionally increasing die size, as the same converter infrastructure serves multiple functions.
Solution Approach 2:
The system dynamically activates only the boost converter circuits needed for the currently accessed memory array, rather than having all converters continuously active. This dynamic operation reduces the effective area required for voltage boosting functionality, allowing multiple converters to be integrated without proportionally increasing die size while maintaining voltage uniformity.
3Area of stationary object
If boost converters are placed far from memory arrays to reduce die size, then manufacturing cost is reduced, but voltage ramp rate consistency and read access speed deteriorate
Solution Approach 1:
The memory device is segmented into multiple independent voltage boosting domains, each with its own boost converter circuit positioned adjacent to the served memory array. This segmentation enables compact integration of converters near their target arrays, maintaining fast read access speeds and consistent voltage ramp rates while controlling overall die size through efficient spatial organization.
4Device complexity
If a fixed voltage boosting scheme is used, then device complexity is reduced, but adaptability to different memory array distances deteriorates
Solution Approach 1:
The voltage boosting system employs dynamic control where each boost converter circuit can be independently activated or deactivated based on which memory array is being accessed. This dynamic switching capability, controlled by circuitry that determines the accessed array's location, provides adaptability to different array positions without requiring complex adjustable voltage parameters, thus maintaining manageable device complexity while achieving high adaptability.
Solution Approach 2:
The system incorporates feedback mechanisms where the address decoding circuitry identifies which memory array is being accessed and uses this information to selectively activate the appropriate boost converter circuit. This feedback-based control ensures that the voltage boosting is adaptively applied to the correct array regardless of its position, providing versatility without requiring complex adjustable parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains uniform read access speed and reliability across all memory arrays while optimizing die size and storage density, preventing voltage overshoot and ensuring efficient data access operations.
Implementation Method 1
a capacitor coupled between a ground line and a voltage supply line VDD, the capacitor to be charged between the ground line and the voltage supply line VDD, the capacitor to provide a boosted voltage between the ground line and a boosted line to the memory array when the memory array is accessed
Data Source
AI summary
A memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost converters, and a switch. When one of the memory arrays is accessed, the switch either couples the boost converters together or does not couple the boost converters together based on the distance of the memory array being accessed from the boost converters.