Nonvolatile Memory Serial I/O Channel Reduction
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Solution Overview
Problem
The limited number of channels in existing testers restricts the simultaneous testing of a large number of dies on a wafer, necessitating a method to minimize channel connections for efficient data input and output during testing.
Innovation Solution
A nonvolatile memory device with a clock input stage, control signal output unit, and n number of IO stages, along with storage units that temporarily store and sequentially input/output data, allowing for reduced channel connections while maintaining 8-bit data integrity during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all eight IO pins are connected to separate channels of the tester, then data input and output can be performed efficiently, but the number of dies that can be tested simultaneously is limited due to the fixed number of tester channels
Solution Approach 1:
The patent merges multiple IO pin connections into a single channel by implementing a serial communication interface. Instead of connecting each of the eight IO pins to separate tester channels, the patent combines their functions into a single serial data path that can sequentially transmit all necessary data bits, thereby reducing the number of channel connections required while maintaining full data input and output capability
Solution Approach 2:
The patent introduces dynamic control signals (such as bit significance indicators and data transfer control signals) that enable a single static channel connection to dynamically perform the functions of multiple channels. The serial interface dynamically shifts between different data bit positions and transfer modes, allowing one physical connection to replace multiple simultaneous connections
2Productivity
If the number of channel connections is reduced to test more dies, then more dies can be tested simultaneously, but the data input and output process becomes more complex
Solution Approach 1:
The patent implements preliminary action by pre-organizing data into serial format with embedded control information before transmission. The data to be transferred is prepared in advance with bit significance indicators and control signals already integrated, so that during the actual transfer process, no additional complex routing or switching is needed - the serial interface simply transmits the pre-packaged data stream
Solution Approach 2:
The patent introduces a serial interface circuit as an intermediary between the tester channel and the internal data paths. This intermediary component handles the complexity of data routing, bit repositioning, and control signal generation, shielding the rest of the system from complexity while enabling efficient data transfer through a single channel connection
Data Source
AI summary
A nonvolatile memory device includes a clock input stage configured to receive a clock signal for a test, a control signal output unit configured to output data input-output (IO) control signals according to the clock signal, n number of IO stages for data IO, and n number of storage units connected to the respective n number of IO stages and configured to temporarily store data to be exchanged between the respective n number of IO stages and internal circuits according to the respective data IO control signals. The n number of storage units are further commonly connected to a first IO stage of the n number of IO stages and configured to sequentially input or output data through the first IO stage in a test mode according to the respective data IO control signals.