Partial Pre-Programming Nonvolatile Memory Erase Time Reduction
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Solution Overview
Problem
The existing erase procedures for memory cells are time-consuming due to the need for pre-programming, which differentiates between memory cells in erased and programmed states, leading to an undesirably wide distribution of threshold voltages and prolonged erase times.
Innovation Solution
An integrated circuit with a nonvolatile memory array and control circuitry that performs a pre-program phase only on a subset of memory cells within a pre-program region, skipping pre-programming of others, followed by an erase phase that addresses all memory cells, including those not pre-programmed, to reduce erase time and voltage distribution issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If all memory cells in the erased state are pre-programmed to a programmed state, then the distribution of threshold voltages is narrowed, but the erase time is significantly prolonged
Solution Approach 1:
The patent applies partial pre-programming by selecting only a first set of memory cells from the erased state for pre-programming, rather than programming all erased cells. This partial action maintains acceptable threshold voltage distribution while significantly reducing the time penalty associated with complete pre-programming of the entire memory array.
Solution Approach 2:
The patent segments the erased memory cells into different sets: a first set that is pre-programmed and a second set that is not pre-programmed. This segmentation allows the erase operation to proceed efficiently while still applying pre-programming benefits to the critical first set of cells, thereby resolving the contradiction between threshold voltage distribution and erase time.
2Manufacturing precision
If memory cells in erased state are pre-programmed while memory cells in programmed state are not pre-programmed, then threshold voltage distribution is improved, but the erase procedure becomes lengthy
Solution Approach 1:
The invention implements partial pre-programming where only a first set of erased memory cells is pre-programmed, rather than all erased cells. This approach maintains sufficient threshold voltage distribution control while avoiding the excessive time consumption of complete pre-programming, thereby improving erase procedure speed without completely sacrificing threshold voltage precision.
Solution Approach 2:
The patent changes the parameter of pre-programming application from universal (all erased cells) to selective (first set of erased cells). By modifying which cells receive the pre-programming treatment, the system achieves a balance between threshold voltage distribution quality and erase procedure efficiency, resolving the contradiction between precision and productivity.
3Manufacturing precision
If pre-programming is performed on memory cells, then threshold voltage distribution is narrowed, but the overall erase procedure duration increases
Solution Approach 1:
The patent applies partial pre-programming to only a first set of erased memory cells rather than all erased cells. This selective approach maintains adequate threshold voltage distribution narrowing while significantly reducing the duration added to the erase procedure by pre-programming, thus resolving the contradiction between precision and time duration.
Solution Approach 2:
The patent performs preliminary pre-programming action on a selected first set of erased memory cells before the main erase operation. By applying this preliminary action selectively rather than universally, the system achieves the beneficial threshold voltage distribution narrowing while minimizing the time penalty, effectively managing the contradiction between precision improvement and procedure duration.
Data Source
AI summary
Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.