Sudden Power Off Detection Circuit for Nonvolatile Memory
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Solution Overview
Problem
Semiconductor memory devices are vulnerable to data corruption and damage due to sudden power off, leading to erroneous programming and potential device failure, necessitating an effective sudden power off detection circuit to mitigate these issues.
Innovation Solution
A nonvolatile memory device incorporating a sudden power off detection circuit with a sensing cell, first and second drivers, and a comparison cell, where the program state of the sensing cell changes based on the timing and order of driver power-off, allowing the circuit to differentiate between sudden and normal power off conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sudden power off detection circuit is added to the memory device, then data integrity is improved and sudden power off can be detected independently, but device complexity increases
Solution Approach 1:
The detection circuit is segmented into distinct functional blocks: first driver circuit, second driver circuit, sensing cell, and comparison cell. Each segment performs a specific function in the detection sequence, allowing the complex detection task to be divided into manageable, modular components that can be independently designed and analyzed.
Solution Approach 2:
The sensing cell acts as an intermediary element between the driver circuits and the comparison cell. It receives voltage inputs from both drivers and translates them into a detectable program state, serving as a mediator that converts electrical signals into a form suitable for comparison and interpretation.
2Measurement precision
If multiple driver circuits and sensing cells are used to detect sudden power off, then detection accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
Different parts of the detection circuit have specialized local properties: the first driver circuit provides a first voltage with specific timing characteristics, the second driver circuit provides a second voltage with different timing characteristics, and the sensing cell is designed to respond differently to each. This local differentiation enables precise detection of power off conditions while maintaining clear functional boundaries that simplify manufacturing.
Solution Approach 2:
The circuit detects sudden power off by monitoring changes in voltage parameters (first voltage and second voltage) applied to the sensing cell at different times. The detection mechanism relies on observing how the program state of the sensing cell changes based on which voltage is removed first, using parameter changes in voltage timing and magnitude as the detection basis.
3Adaptability or versatility
If the sensing cell program state changes based on driver power-off timing, then sudden power off detection capability is improved, but device complexity increases
Solution Approach 1:
The sensing cell is pre-configured with the capability to respond to different power off scenarios before actual detection is needed. During normal operation, both driver circuits are active and establish baseline conditions. When power off occurs, the pre-configured sensing cell automatically responds based on the timing and sequence of voltage removal, eliminating the need for complex real-time decision logic.
Solution Approach 2:
The detection circuit uses feedback from the sensing cell's program state to determine whether sudden power off occurred. The comparison cell receives information about the sensing cell state and uses this feedback to generate the final detection output, creating a closed-loop system that automatically adjusts its interpretation based on the observed program state changes.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.