Monolithic 3D NAND Floating Gate Uniformity via Selective Etching
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Solution Overview
Problem
Conventional three-dimensional NAND memories face challenges with slow erase times, less than desirable data retention, and charge spreading due to the use of silicon nitride charge storage dielectric layers, and difficulty in achieving uniform floating gate thicknesses in high aspect ratio structures.
Innovation Solution
The method involves selective wet etching between different silicon dioxide films and selective oxidation/removal of polysilicon floating gate material from the back side to fabricate monolithic three-dimensional NAND strings with uniform floating gate thicknesses, using materials like polysilicon, silicon-germanium, or metal silicide that can be oxidized or selectively etched, and forming control gate electrodes over blocking dielectrics in recesses between adjacent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride charge storage dielectric layers are used in conventional three-dimensional NAND memories, then charge storage capability is provided, but data retention and erase times are slow and charge spreading occurs
Solution Approach 1:
The patent changes the material parameter from silicon nitride to polysilicon floating gate, fundamentally altering the charge storage mechanism. This material substitution enables faster erase times and improved data retention by eliminating charge spreading effects inherent in dielectric-based charge storage
Solution Approach 2:
The patent selectively removes portions of the polysilicon floating gate material through the back side opening to create discrete floating gate segments. This selective discarding of material enables precise control over charge storage regions, improving data retention by preventing charge spreading between adjacent memory cells
2Ease of manufacture
If conventional processes are used to form active regions in three-dimensional NAND strings, then active regions are created, but the process is difficult and time consuming involving repeated formation of sidewall spacers and etching
Solution Approach 1:
The patent forms the complete alternating stack of first and second material layers before any etching or spacer formation. This preliminary stacking approach allows subsequent selective removal processes to create active regions in a single step rather than requiring repeated cycles of spacer formation and etching
Solution Approach 2:
The patent segments the floating gate layer into discrete portions by selectively removing material through the back side opening. This segmentation creates isolated floating gate segments between control gate electrodes, simplifying the overall fabrication process by enabling direct formation of functional regions without complex spacer-based patterning
3Manufacturing precision
If conventional methods are used to form floating gates in high aspect ratio structures, then floating gates are formed, but uniform floating gate thicknesses cannot be achieved
Solution Approach 1:
The patent forms the floating gate layer throughout the entire high aspect ratio structure first, then selectively removes portions from the back side. This inverted approach—forming the complete structure then subtracting material rather than building up the final shape directly—enables uniform thickness throughout the high aspect ratio structure while creating the desired discrete segment pattern
Solution Approach 2:
The patent replaces complex mechanical spacer-based patterning with a chemical etching process that selectively removes polysilicon material through the back side opening. This substitution of etching for mechanical spacer formation simplifies the process and achieves uniform floating gate thickness by relying on the inherent uniformity of the deposited polysilicon layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of three-dimensional NAND strings by enhancing data retention and erase times, reducing charge spreading, and allowing for the fabrication of NAND strings with uniform floating gate thicknesses, leading to more efficient charge storage and improved device performance.
Implementation Method 1
selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers
Implementation Method 2
reacting the metal layer with the exposed portions of the silicon floating gate to form discrete silicide floating gate segments
Implementation Method 3
oxidizing or removing the exposed remaining silicon portions of the silicon floating gate layer
Data Source
AI summary
A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.