3D NAND Inter-Deck Plugs Using Single-Crystal Silicon
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Solution Overview
Problem
Current 3D NAND memory devices face limitations in density and performance due to the use of polysilicon inter-deck plugs and source layers, which have low carrier mobility, and the hybrid bonding process requires high alignment accuracy and can introduce voids, increasing fabrication complexity and cycle time.
Innovation Solution
The use of single-crystal silicon layers transferred via a de-bonding process for forming inter-deck plugs and source layers, replacing polysilicon with single-crystal silicon to enhance carrier mobility and bonding strength, and forming interconnects on dedicated donor substrates to reduce fabrication cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon inter-deck plugs and source layers are used in 3D NAND memory devices, then fabrication process is simpler, but carrier mobility is low and performance is limited
Solution Approach 1:
The patent changes the material parameter from polysilicon to single-crystal silicon for inter-deck plugs and source layers. This material substitution fundamentally alters the electrical properties, providing higher carrier mobility and improved device performance while maintaining compatibility with existing fabrication processes through transferred wafer bonding technology.
Solution Approach 2:
The patent employs a composite structure combining single-crystal silicon layers with dielectric layers and conductor layers. The single-crystal silicon provides superior electrical transport properties, while the composite structure integrates multiple functions including inter-deck connections, source regions, and interconnect formation, resolving the contradiction between material performance and fabrication complexity.
2Reliability
If hybrid bonding process is used to join wafers, then wafer bonding is achieved, but high alignment accuracy is required and voids may be introduced
Solution Approach 1:
The patent performs preliminary patterning of alignment marks and bonding interface structures on the donor wafer before the bonding process. This preliminary action establishes precise registration features that guide the bonding alignment, reducing the stringency of real-time alignment requirements and minimizing the risk of void formation during wafer joining.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the single-crystal silicon layer and the underlying structure. This intermediary layer provides a compliant bonding interface that accommodates thermal expansion differences and stress mismatches, enabling robust bonding while reducing sensitivity to alignment errors and preventing void formation.
3Productivity
If interconnects are formed on dedicated donor substrates, then fabrication cycle time is reduced, but additional substrate handling is required
Solution Approach 1:
The patent segments the fabrication process by forming interconnects on dedicated donor substrates separately from the main memory stack fabrication. This segmentation allows parallel processing of different device components, reducing overall fabrication cycle time. The segmented interconnect structures are subsequently integrated through wafer bonding, managing substrate handling complexity through modular assembly.
Solution Approach 2:
The patent merges the separately fabricated interconnect structures with the main memory stack through wafer bonding. This merging step integrates the parallel-produced components into a unified device structure, achieving the productivity benefits of parallel fabrication while maintaining device structural integrity and electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases cell storage capacity and performance at inter-deck joints, improves yield, and reduces fabrication complexity and cycle time by using single-crystal silicon with higher carrier mobility and bonding strength, while allowing for flexible vertical arrangement of device structures.
Implementation Method 1
The second substrate and the first substrate are bonded in a face-to-face manner
Implementation Method 2
A single-crystal silicon layer is split from the second substrate along the heterogeneous interface in the second substrate to leave the single-crystal silicon layer bonded on the first dielectric deck
Data Source
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Figure 1C
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck above the substrate, a first channel structure, a first inter-deck plug above and in contact with the first channel structure, a second memory deck above the first inter-deck plug, and a second channel structure above and in contact with the first inter-deck plug. The first memory deck includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure extends vertically through the first memory deck. The first inter-deck plug includes single-crystal silicon. The second memory deck includes a second plurality of interleaved conductor layers and dielectric layers. The second channel structure extends vertically through the second memory deck.