3D NAND Memory Device Program Disturbance Suppression
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Solution Overview
Problem
In 3D NAND flash memory devices, the program disturbance phenomenon occurs due to high voltage application, leading to deformation of threshold voltages in multi-level cells, resulting in non-ideal data states and reduced read margins.
Innovation Solution
A memory device and programming method that utilize a voltage generator to produce precharge, program, and negative voltages, and a control logic circuit to manage program operations through multiple loops, applying negative voltage to unselected select transistors during program execution to suppress program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to program memory cells in 3D NAND flash, then programming operation is enabled, but program disturbance occurs causing threshold voltage deformation
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging unselected bit lines to a high voltage level before the programming operation. This pre-charging creates a protective high potential in unselected regions, preventing electron injection and threshold voltage deformation in unselected memory cells during the high-voltage programming pulse. The harmful effect (electron leakage to unselected cells) is counteracted in advance by establishing a protective voltage barrier.
Solution Approach 2:
The patent implements local quality by differentiating voltage levels applied to different regions of the memory array. Selected bit lines receive the programming voltage while unselected bit lines receive a different (higher) voltage level. This spatial differentiation ensures that only selected memory cells undergo programming, while unselected cells are protected through their different voltage condition, thereby preventing program disturbance locally in unselected regions.
2Manufacturing precision
If multiple program loops are performed to achieve target threshold voltage, then programming precision is improved, but program time increases
Solution Approach 1:
The patent applies preliminary action by performing pre-charging of unselected bit lines before each program loop. This pre-charging step prepares the memory array in advance for the upcoming programming operation, ensuring that unselected cells are already in a protective state. By performing this preparation action beforehand, the actual programming loops can proceed more efficiently without needing to repeatedly compensate for disturbance effects, thereby reducing total program time while maintaining precision.
Solution Approach 2:
The patent implements feedback through verification read operations performed between program pulses. After each program loop, the threshold voltage of selected memory cells is verified to determine whether the target state has been achieved. This feedback mechanism allows the control logic to adjust subsequent programming pulses accordingly, stopping the program loops early when the target is reached, thus avoiding unnecessary iterations and reducing overall program time while ensuring precision.
3Measurement precision
If verification operations are performed between program pulses, then programming accuracy is verified, but operation duration increases
Solution Approach 1:
The patent applies periodic action by performing verification operations at specific intervals between program pulses rather than continuously. The verification is conducted periodically after each program pulse or program loop to check whether the target threshold voltage has been achieved. This periodic verification approach ensures programming accuracy is monitored at critical stages while avoiding the time penalty of continuous verification, as the verification only occurs when necessary to confirm program completion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses program disturbance, maintaining ideal threshold voltage distributions and enhancing program characteristics by preventing electron leakage and maintaining high channel potentials.
Implementation Method 1
the control logic circuit is further configured to provide the negative voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistors included in a plurality of unselected cell strings from among the plurality of cell strings, during the program execution duration
Data Source
AI summary
A memory device, including: a memory cell array including a plurality of cell strings; a voltage generator configured to generate a precharge voltage, a program voltage, and a negative voltage; and a control logic circuit configured to control a program operation for programming a threshold voltage of a selected memory cell to have a target state, wherein the program operation is performed using a plurality of program loops, based on a voltage increment of the program voltage, and wherein each program loop from among the plurality of program loops includes a precharge duration and a program execution duration, wherein the control logic circuit is further configured to provide the negative voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistors included in a plurality of unselected cell strings from among the plurality of cell strings, during the program execution duration.