Read-Only Memories TRIZ Cases

A flash memory control circuit adjusts read threshold voltages based on measured cell temperatures to compensate for charge accumulation variations.

A semiconductor device isolates passed planes during failed multi-plane erase operations to prevent unnecessary re-processing of functional memory cells.

Partitioning a memory array into single level and multi-level portions balances data storage density with operational flexibility for sensitive and user data.

Non-bijective mapping reduces voltage levels in flash memory, improving data retention and throughput while maintaining storage density.

A nonvolatile memory recovery system adjusts voltage boundaries to correct threshold drift in multi-bit cells.

Floating select lines suppresses gate-induced-drain-leakage current, preventing channel potential increases that cause inaccurate threshold voltage readings.

Merges plane selection with column addressing in nonvolatile memory devices, eliminating separate input cycles and reducing operation time.

A NAND flash controller recalculates error-correcting codes before writing data to destination blocks.

A memory sub-system controller determines read levels using block-specific voltage distribution parameters stored in a mapping table.

Compare circuit loads and matches predetermined data with complementary sets to resolve unstable voltage fluctuations during flash memory power on.

Dedicated nonvolatile erase status flags allow controllers to detect and complete interrupted erase cycles, preventing data corruption during power loss.

A memory sensing system uses pre-charge voltage on bit lines to improve multi-level cell state detection accuracy.

A memory controller executes parallel reads across multiple planes to accelerate data retrieval operations.

A multi-functional terminal supplies erase program voltage to an integrated memory circuit, eliminating embedded charge pumps and reducing silicon surface area.

A memory controller segments input data into groups with associated parity rows to enable granular error detection and correction.

A voltage generation circuit uses two charge pumps with distinct characteristics to supply different voltage levels to a memory cell array.

A semiconductor memory device uses a control unit to lock temperature-based read voltage compensation values during operations.

Dynamic page margin adjustment balances bit error rates across logical page types, extending memory endurance without excessive control complexity.

A semiconductor memory voltage circuit charges a condenser to maintain stable internal power source levels.

A memory controller calculates a dynamic start voltage based on page data to optimize programming speed in flash devices.

A multilevel resistive memory structure segments switching layers with defective films to form conductive filaments for four distinct resistance states.

A flash memory counter update method initializes pages with all possible values to enable rapid byte-level state changes.

A memory device performs write-in-place operations by erasing a single page and applying distinct voltage biases to program specific cells.

A memory driving device uses a voltage detecting circuit and switch array to regulate output voltage waveforms in real time.

Applying distinct bit line voltages based on data type resolves write time versus reliability trade-offs in NAND flash memory.

Grouping word lines for separate soft program operations narrows the threshold voltage distribution range while maintaining wider margins between states.

A flash memory program method biases one word line with a setup voltage while driving another in a program or verification phase.

Segmented word line control allows byte-level erasure in flash memory, reducing voltage regulator complexity and enabling dual functionality.

A memory device uses a voltage code controller to generate program and pass voltages based on program loop counts.

Asymmetric terminal spacing on a memory card substrate minimizes signal transfer paths to enable high-speed data operation.

Flash memory controllers adjust sensing voltages based on detected cell quantities to resolve threshold voltage drift and improve reading accuracy.

Multi level inhibit scheme adjusts programming speed across memory cells using varied gate-to-channel potentials.

A semiconductor device applies a pre-program voltage to word lines to generate a fringe field that injects electrons into space regions.

A voltage generation circuit uses a noise attenuation circuit and multi-stage pump to produce target voltages.

A semiconductor memory device uses a voltage trimming unit and nonvolatile memory cells to store control signals for accurate internal voltage generation.

Applying read setup bias to 3D memory cells while disabling current flow maintains threshold voltage consistency and reduces power loss.

Segmented cell gate lines with interconnection units enable parallel signal paths, reducing transmission delay caused by high resistance and capacitance.

Connecting power supply outputs to decoders stabilizes regulator circuits, reducing chip area without compromising memory operations.

A programmable resistance memory device detects margin cells by measuring time intervals during sensing operations to determine data values.

A 3D NAND memory device applies negative voltage to unselected select transistors during program execution.

Segmenting the memory array and applying localized voltages enables selective erasure, preventing erroneous data loss from collective block operations.