3D Memory Cell Gate Line Segmentation for Signal Delay Reduction
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Solution Overview
Problem
The existing memory devices face delays in signal transmission due to high resistance and capacitance in word lines, leading to reduced operating speed and increased failure rates, especially in 3D memory arrays where signals take longer to reach cell transistors, affecting overall device performance.
Innovation Solution
The implementation of a memory device with a 3D memory cell array that includes cell transistors configured to receive signals through multiple paths, utilizing interconnection units to connect cell gate lines at both ends, reducing signal delay and enhancing operating speed, and incorporating a row decoder to apply selection and non-selection voltages independently to ground and string selection lines, thereby reducing capacitance and improving signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If signals are transmitted through single path in conventional memory devices, then the structure is simple, but signal transmission delay increases due to high resistance and capacitance
Solution Approach 1:
The word line is divided into multiple segments (first word line segment and second word line segment) that are electrically connected through different paths. This segmentation allows signals to reach cell transistors through multiple parallel routes, reducing transmission delay caused by high resistance and capacitance in single long word lines.
Solution Approach 2:
The patent introduces a third-dimensional vertical structure where cell transistors are stacked above the substrate. The interconnection units are positioned at different vertical levels to connect cell gate lines, creating multiple spatial paths for signal transmission. This vertical dimensionality adds alternative signal routes without increasing planar area, effectively reducing signal transmission delay.
2Reliability
If ground selection lines are electrically connected to reduce capacitance, then capacitance decreases, but signal interference increases
Solution Approach 1:
The ground selection lines are segmented into first and second ground selection lines that are electrically insulated from each other. This segmentation prevents signal interference between different string selections while still allowing each ground selection line to be independently controlled. The insulation between ground selection lines eliminates capacitive coupling interference, improving signal transmission reliability.
Solution Approach 2:
The patent implements dynamic control of ground selection lines where the row decoder can independently select and activate different ground selection lines based on the specific string being accessed. This dynamic switching capability allows the system to optimize signal paths and avoid interference by activating only the necessary ground selection line during each operation.
3Reliability
If multiple interconnection units are used to provide alternative paths, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The interconnection units are designed with multi-functionality to serve multiple purposes: they connect cell gate lines horizontally, provide vertical interlayer connections, and enable alternative signal paths. By making these interconnection structures universal and multi-functional, the patent reduces the need for separate dedicated components for each function, thereby simplifying the overall manufacturing process while maintaining reliability.
Data Source
AI summary
A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.