Memory Array Partitioning for Single and Multi-Level Cell Modes
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Solution Overview
Problem
Current memory devices lack flexibility in addressing memory cells, as they are typically configured to operate in either single level or multi-level modes without the ability to dynamically partition the memory array based on user instructions, limiting data storage density and operational flexibility.
Innovation Solution
A partitioning system is introduced that configures a memory array to operate in both single level and multi-level modes, using a programmable address pointer to partition the array into different portions, allowing for flexible data storage and addressing formats, enabling efficient data transfer between these modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are configured to operate in either single level or multi-level modes, then data storage density can be improved, but operational flexibility and addressing capability are reduced
Solution Approach 1:
The memory array is divided into multiple portions (first portion and second portion) that can be independently addressed and operated. The partitioning system enables selective access to different portions, allowing single level mode for certain data and multi-level mode for other data within the same physical memory structure.
Solution Approach 2:
The memory device transitions from a static configuration to a dynamic one where the operational mode can be changed based on user instructions. The partitioning system allows the memory array to be reconfigured between single level and multi-level modes, providing adaptability while maintaining high storage density.
2Adaptability or versatility
If a partitioning system is introduced to enable both single level and multi-level modes, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The partitioning system is designed to work within the existing memory array structure, enabling a single device to perform multiple functions (single level mode, multi-level mode, and data transfer between modes) without requiring separate memory devices or completely new architectural designs.
Solution Approach 2:
The partitioning system acts as an intermediary layer between the user and the memory array. It manages the complexity of mode switching and data transfer by providing a unified interface that abstracts the underlying physical structure, making the system easier to use while maintaining flexibility.
3Quantity of substance
If data is stored in multi-level cells to increase storage density, then data storage capacity is improved, but reliability and data accuracy may be compromised
Solution Approach 1:
Different portions of the memory array can be assigned different operational characteristics. Sensitive or critical data can be stored in single level mode portions for high reliability, while less critical data can be stored in multi-level mode portions for high density, allowing each region to have optimized local properties.
Solution Approach 2:
The memory array is segmented into portions that can be independently configured. This segmentation allows the system to balance between reliability and density by directing different types of data to appropriate segments, preventing the reliability issues from affecting the entire memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides enhanced data storage density and operational flexibility by allowing sensitive data to be stored in single level cells while user data can be stored in multi-level cells, meeting high reliability standards and optimizing memory usage.
Implementation Method 1
The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure
Implementation Method 2
The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure
Implementation Method 3
Programming with hot electron injection involves applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. When a resulting electric field is high enough, electrons collect enough energy to be injected from the source onto the control gate
Implementation Method 4
The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide
Implementation Method 5
A read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell
Data Source
AI summary
A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.