Flash Memory Data Loading Error Detection Circuit
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Solution Overview
Problem
During the power on sequence of a flash memory device, data reading from nonvolatile memory cells is unstable due to fluctuating device voltage, leading to potential errors in loading important control information.
Innovation Solution
A semiconductor device with two groups of nonvolatile memory cells and data registers, along with a compare circuit that loads and compares predetermined data and complementary data to ensure accurate loading by verifying matches before proceeding, using transistors for comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read from nonvolatile memory cells during power on sequence, then control information is loaded to enable device function, but data reading becomes unstable due to fluctuating device voltage
Solution Approach 1:
The patent applies preliminary action by performing error detection and comparison operations before final data acceptance. The system reads data multiple times during power-on sequence, compares each reading against previous readings, and only accepts data when consistency is confirmed. This preliminary verification process ensures that unstable readings caused by voltage fluctuations are rejected before they can corrupt the loaded control information.
Solution Approach 2:
The patent implements feedback by using the compare circuit to continuously monitor data readings and provide feedback to the control circuit. When data readings differ between successive reads, the compare circuit detects this discrepancy and triggers another read attempt. This feedback loop continues until consistent data is obtained, thereby compensating for the initial instability caused by voltage fluctuations and ensuring reliable data loading.
2Reliability
If error detection and comparison operations are performed during power on sequence, then data accuracy is improved, but device operation time is increased
Solution Approach 1:
The patent applies partial action by performing error detection and comparison operations selectively rather than indefinitely. The system limits the number of comparison iterations and uses thresholds to determine when sufficient verification has been achieved. This approach obtains adequate data accuracy through partial verification rather than exhaustive checking, thereby reducing the time penalty while maintaining reliability.
Data Source
AI summary
A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.