Flash Memory Architecture with Byte-Level Erasure Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory systems cannot erase data on a byte-by-byte basis, leading to increased complexity in voltage regulator circuitry and limitations in providing both flash and EEPROM functionalities using the same die manufacturing process.
Innovation Solution
A flash memory device architecture that allows for byte-level erasure by modifying the connection and control of word lines, source lines, and bit lines, enabling independent operation of selected byte pairs without affecting other bytes or byte pairs, thereby emulating EEPROM functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If flash memory systems use traditional sector erasure methods, then erasure operations can be performed on entire sectors, but byte-by-byte erasure is not possible and voltage regulator circuitry complexity increases
Solution Approach 1:
The patent segments the word line control into multiple independently controllable word line select signals (WL0SEL, WL1SEL, etc.), allowing selective activation of individual word lines. This segmentation enables byte-by-byte erasure by controlling which specific word lines receive high voltage during erase operations, thereby erasing only the desired bytes rather than entire sectors.
Solution Approach 2:
The patent implements local quality by applying different voltage conditions to different parts of the memory array simultaneously. Through the use of word line select signals and source line select signals, specific regions (bytes) can be subjected to erase voltages while other regions remain at normal operating voltages, enabling localized byte-by-byte erasure without affecting the entire sector.
2Adaptability or versatility
If flash memory systems provide both flash and EEPROM functionalities, then memory versatility is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent achieves universality by designing a single memory cell structure and control circuitry that can operate in both flash mode and EEPROM mode. The same memory cells, word lines, bit lines, and control logic can perform sector erasure (flash mode) or byte-by-byte erasure (EEPROM mode) by simply changing the activation patterns of the word line select signals and source line select signals, eliminating the need for separate manufacturing processes.
Solution Approach 2:
The patent implements dynamic functionality switching through controllable select signals. The word line select signals (WL0SEL, WL1SEL, etc.) and source line select signals (SL0SEL, SL1SEL, etc.) can be dynamically activated or deactivated to switch between flash and EEPROM operational modes, allowing the system to adapt its erasure granularity (sector-level or byte-level) based on operational requirements without hardware changes.
3Measurement precision
If independent byte pair operation is enabled, then erasure precision is improved, but control signal complexity increases
Solution Approach 1:
The patent segments the control signals into word line select signals (WL0SEL, WL1SEL, etc.) and source line select signals (SL0SEL, SL1SEL, etc.), where each pair of select signals controls a specific byte pair. This segmentation allows precise control over which byte pairs are erased by activating only the relevant select signals, achieving byte-level precision while maintaining systematic control.
Solution Approach 2:
The patent introduces word line select signals and source line select signals as intermediary control elements between the control logic and the memory cells. These intermediary signals simplify the control complexity by providing a systematic interface: activating a specific WLxSEL and SLxSEL pair selectively controls the corresponding byte pair, abstracting the complex underlying control requirements into simple signal activation patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables byte-by-byte erasure and programming in flash memory systems, reducing complexity in voltage regulation and allowing for the integration of flash and EEPROM functionalities using the same manufacturing process, enhancing memory density and sector erasability.
Implementation Method 1
a charge pump circuit used to provide increased voltages for program and erase operations for the memory arrays
Implementation Method 2
The cell 110 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 122 and zero volts to the bit line and source line
Implementation Method 3
The cell 110 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line 114, a small voltage on the word line 122, and a programming current on the bit line 120
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.