Multi Level Inhibit Scheme for Flash Memory Programming

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Flash memory devices face issues with program disturb and increased programming time due to the need for additional programming pulses, which can cause undesirable shifts in threshold voltages of memory cells that have already reached their intended levels, especially in Multilevel Cell (MLC) memory configurations.

Innovation Solution

A multi-level inhibit scheme is employed, where the programming speed of memory cells is adjusted based on the required threshold voltage shift by varying the gate-to-channel potential, allowing cells to be programmed simultaneously at different rates, thereby reducing the number of programming pulses and mitigating program disturb effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional programming pulses are applied to ensure all memory cells reach their threshold voltage, then programming completeness is improved, but program disturb increases and programming time extends

Engineering Contradiction:

Improveprogramming completenessVSAvoidprogram disturb

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different inhibit voltages to different bit lines based on the specific programming status of memory cells connected to each bit line. Memory cells that have reached their target threshold voltage receive a stronger inhibit voltage to prevent further programming, while cells that need more programming receive a weaker or no inhibit voltage. This localized differentiation resolves the contradiction by allowing programming completeness without causing program disturb to already-programmed cells.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the inhibit voltage parameter applied to different bit lines during the programming process. By changing the voltage level based on verification results, the system can stop programming for specific bit lines once their memory cells reach the target state, thereby preventing program disturb while ensuring all cells are properly programmed.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If additional programming pulses are applied to ensure all memory cells reach their threshold voltage, then programming completeness is improved, but overall programming time increases

Engineering Contradiction:

Improveprogramming completenessVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary verification after initial programming pulses to identify which bit lines have memory cells that have reached their target threshold voltage. By verifying the programming status early and applying inhibit voltages to completed bit lines, the system avoids wasting additional programming time on cells that are already programmed, thus reducing overall programming time while ensuring completeness.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent divides the memory array into multiple bit line segments and independently controls the programming process for each segment. By verifying and applying inhibit voltages to individual bit lines based on their specific programming status, the system can proceed with programming for remaining bit lines without being constrained by already-completed segments, thereby optimizing overall programming time.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If uniform programming voltage is applied to all memory cells on a word line, then device complexity is reduced, but manufacturing precision of threshold voltage distribution deteriorates

Engineering Contradiction:

Improveprogramming control complexityVSAvoidthreshold voltage distribution precision

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables memory cells on a common word line to complete programming more closely in time, reducing overall programming time and minimizing program disturb issues while maintaining reliable threshold voltage distributions.

Implementation Method 1

Programming of flash memory cells is accomplished by applying a high programming voltage to the word lines of the memory array in order to shift the threshold voltages of the memory cells

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

The control gates of memory cells of a given row share the same control signal, which is often referred to as a word line

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS8422297B2Multi level inhibit scheme

Publication Date: 2013.04.16 MICRON TECHNOLOGY INC

AI summary

Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.