Memory Controller Parallel Read Error Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in efficiently reading and writing data across multiple planes due to issues like word line short-circuits, which can lead to uncorrectable errors and data loss during multi-plane operations.
Innovation Solution
The memory system employs a controller that performs parallel reads and writes across multiple planes, using error correction codes and restore data to correct errors and maintain data integrity, and includes a leak word line table to detect and manage current leaks, allowing for single plane reads and writes when multi-plane operations fail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel reads and writes are performed across multiple planes to improve productivity, then data retrieval and writing speed increase, but word line short-circuits can occur leading to uncorrectable errors and data loss
Solution Approach 1:
The system performs preliminary actions by generating and storing restore data before multi-plane operations, and by detecting potential word line short-circuits before they cause data loss. The controller prepares error correction codes and restore data in advance, allowing it to recover from failures that occur during parallel operations across multiple planes.
Solution Approach 2:
The system implements beforehand cushioning by creating restore data as a protective buffer against potential data loss from word line short-circuits. This restore data acts as a safety net that compensates for errors that may occur during multi-plane operations, ensuring data integrity even when parallel operations cause harmful effects.
2Reliability
If error correction codes and restore data are used to correct errors and maintain data integrity, then reliability improves, but device complexity increases
Solution Approach 1:
The system creates a copy of data in the form of restore data that can be used for error correction. By generating restore data as a separate copy derived from the original data through XOR operations, the system maintains data integrity without requiring complex redundant storage structures, simplifying the overall device architecture while improving reliability.
3Reliability
If extensive buffer storage is used to maintain data during operations, then data integrity is maintained, but device complexity and resource usage increase
Solution Approach 1:
The system discards the need for extensive buffer storage by using restore data that can be generated on-demand and discarded after use. Instead of maintaining large buffers to hold data during operations, the system creates compact restore data, uses it for error correction when needed, and then discards it, significantly reducing memory resource requirements while maintaining data integrity.
Data Source
AI summary
A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.