Dynamic Page Margin Control for Memory Endurance
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Solution Overview
Problem
Conventional memory sub-systems do not dynamically control or adjust page margins for logical page types, leading to imbalanced bit error rates and reduced endurance across different memory cells.
Innovation Solution
The method involves adjusting the current page margin corresponding to a logical page type based on a modified page margin, using continuous read level calibration (cRLC) and program targeting (PT) operations to equalize valley margins and bit error rates across different logical page types, thereby optimizing the programming distributions and extending the memory system's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory sub-systems do not dynamically control page margins, then device complexity is reduced, but bit error rates become imbalanced and endurance decreases
Solution Approach 1:
The patent implements dynamic page margin control by adjusting program verify targets based on real-time error counts from continuous read level calibration. The system transitions from static manufacturing defaults to dynamic adjustment, where page margins are modified based on measured bit error rates across different logical page types, thereby improving reliability without excessive complexity
Solution Approach 2:
The system uses feedback from error count measurements to adjust page margins. The continuous read level calibration operation provides error count data, which feeds into the program targeting operation that modifies program verify targets. This closed-loop feedback mechanism balances bit error rates across logical page types, enhancing endurance through data-driven adjustments
2Reliability
If page margins are dynamically adjusted, then bit error rates are balanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameters of program verify targets dynamically based on measured error rates. Instead of using fixed manufacturing default values, the system adjusts voltage thresholds and program parameters in response to actual bit error rate measurements, achieving better error rate balance without requiring ultra-precise manufacturing
3Reliability
If continuous read level calibration is performed, then valley margins are equalized, but processing time increases
Solution Approach 1:
The system performs continuous read level calibration periodically during normal memory operations rather than requiring separate dedicated calibration time. The calibration operates in the background during routine read and program operations, equalizing valley margins without significantly impacting overall processing time through efficient periodic execution
Data Source
AI summary
One or more of multiple metrics for multiple logical page types of the memory device are determined. Each of the metrics is indicative of a number of bit errors associated with a particular logical page type of the multiple logical page types. A current page margin associated with a first logical page type of the multiple logical page types is modified to determine a modified page margin based at least in part on a ratio using one or more of the multiple metrics. The current page margin associated with the first logical page type is adjusted in accordance with the modified page margin.