Nonvolatile Memory Write Voltage Control via Local Quality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multi-value NAND flash memory devices face inefficiencies in write operations due to varying numbers of voltage step-ups required for different threshold voltage distributions, leading to prolonged write times and risks of erroneous writes when trying to optimize for all distributions.
Innovation Solution
A nonvolatile semiconductor memory device with a control circuit that applies distinct voltages to bit lines based on the specific data being written, using a data latch circuit, arithmetic circuit, and sense amplifier circuit to manage voltage clamp transistors and apply appropriate voltages to each bit line connected to a common word line, allowing for efficient writing across multiple threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write voltage Vpgm is stepped up in increments to complete the write operation for all threshold voltage distributions, then the write operation can be completed for all data types, but the write time is significantly lengthened
Solution Approach 1:
The patent applies different write voltages to different bit lines based on the specific threshold voltage distribution of the data being written. Instead of using a uniform stepped-up voltage for all memory cells, the control circuit selectively applies appropriate voltages (Vpgm0, Vpgm1, Vpgm2, or Vpgm3) to each bit line, allowing each memory cell to be written optimally without waiting for others to complete sequential voltage steps.
Solution Approach 2:
The patent performs preliminary classification of data to be written into different threshold voltage distribution groups before the write operation. The control circuit determines in advance which voltage level is needed for each bit line based on the data characteristics, and prepares the corresponding voltages beforehand, eliminating the need for sequential voltage stepping during the write operation.
2Productivity
If the write voltage is optimized for specific threshold voltage distributions to reduce write time, then write speed improves, but the risk of erroneous writes increases for other distributions
Solution Approach 1:
The patent ensures write accuracy by matching the write voltage to the specific threshold voltage distribution of each data group. The control circuit applies Vpgm0 for distribution 0, Vpgm1 for distribution 1, Vpgm2 for distribution 2, and Vpgm3 for distribution 3, ensuring each memory cell receives the optimal voltage for its data type, thus preventing erroneous writes while maintaining high write speed.
Solution Approach 2:
The patent incorporates a verify judgment mechanism that checks whether the write operation was successful. The control circuit performs verification after writing and can re-perform the write operation with appropriate voltage adjustments if needed, ensuring write accuracy while maintaining overall write speed through efficient feedback control.
3Quantity of substance
If multi-value storage is implemented to increase memory capacity, then storage density improves, but the complexity of voltage control increases
Solution Approach 1:
The patent segments the voltage control into four distinct levels (Vpgm0, Vpgm1, Vpgm2, Vpgm3) corresponding to four different threshold voltage distributions. This segmentation allows the control circuit to manage multi-value storage by selecting from predefined voltage levels, simplifying the control logic compared to continuous voltage adjustment while still achieving high storage density through multi-bit per cell operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces write time by optimizing voltage application for each memory cell, minimizing the risk of erroneous writes and enabling faster data storage across multiple bits in a single memory cell.
Implementation Method 1
a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell
Data Source
AI summary
A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell. During writing of information to a plurality of the memory cells connected to an identical word line, the control circuit is configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written.