Semiconductor Memory Power Supply Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the larger capacity of the main memory cell array necessitates a larger well area for stabilization, increasing the chip area due to oscillation issues in the regulator circuit when powering the ROM memory cell array, which has a smaller capacity.
Innovation Solution
The output terminal of the power supply circuit is electrically connected to at least one decoder of the higher-capacity memory cell array when powering the lower-capacity ROM memory cell array, utilizing the decoder's capacity as stabilization, thereby reducing the overall chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacity of the memory cell array is smaller (ROM memory cell array), then the chip area can be reduced, but the regulator circuit oscillates more easily requiring a larger well area for stabilization
Solution Approach 1:
The decoders of the first memory cell array serve dual purposes: they function as normal decoders during first memory array operations, and they serve as stabilization capacitors during second memory array operations. This multi-functionality eliminates the need for separate stabilization wells, reducing chip area while maintaining regulator stability.
2Reliability
If the area of the well is increased to obtain large stabilization capacity, then the regulator circuit oscillation is prevented, but the chip area increases
Solution Approach 1:
The invention merges the stabilization function with the existing decoder structures. Instead of adding separate well capacitors, the decoders themselves are utilized as the stabilization element, combining multiple functions into existing components and reducing overall chip area.
3Reliability
If the capacity of the memory cell array is larger (main part memory cell array), then the stabilization capacity is sufficient, but the boosting time is shorter requiring optimized power supply design
Solution Approach 1:
The power supply circuit dynamically switches between different operational modes based on which memory array is being accessed. When the second memory array is active, the circuit configures the output terminal to connect to decoder capacitors for stabilization. This dynamic adaptation allows optimal performance for each memory array type without compromising the other.
Data Source
AI summary
A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines connected to the memory cells; a data program and read control section including a plurality of decoders for, when performing data programming, read or erasure with respect to a corresponding memory cell, selecting, and applying a voltage to corresponding word and bit lines; and a power supply circuit for supplying power to the data program and read control section; wherein when the power supply circuit is to supply power to the second memory cell array, an output terminal of the power supply circuit is electrically connected to at least one of the decoders connected to the first memory cell array.