Semiconductor Storage Selective Data Erasure via Word Line Voltage Control
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Solution Overview
Problem
Current semiconductor storage devices erase data collectively for a block of memory cells, lacking the ability to selectively erase data from individual memory cell transistors, which can lead to inefficient data management and potential errors in threshold voltage distribution.
Innovation Solution
A semiconductor storage device with a memory cell array comprising first and second select transistors and memory cell transistors connected in series, where the threshold voltage of memory cell transistors is increased by applying a voltage lower than the channel voltage to the word line, allowing selective erasure of data stored in connected memory cell transistors while maintaining data in non-connected transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data erasing is performed collectively for a block of memory cells, then the erasing operation is simple to execute, but data management efficiency deteriorates and potential errors in threshold voltage distribution occur
Solution Approach 1:
The patent divides the memory cell array into multiple independently controllable blocks, each with its own word lines. This segmentation allows selective erasing of specific blocks rather than requiring collective erasure of entire memory regions, thereby improving data management efficiency while maintaining operational simplicity through block-level control.
Solution Approach 2:
The patent applies different voltage conditions to different word lines to achieve localized erasure effects. By controlling the voltage applied to specific word lines (first voltage for erasure, second voltage for non-erasure), the system can selectively erase data in specific memory cell transistors while preserving data in others, enabling precise data management at the local level.
2Device complexity
If data erasing is performed collectively for a block of memory cells, then the control mechanism is simple, but data accuracy deteriorates due to potential erroneous data loss
Solution Approach 1:
The memory cell array is segmented into multiple blocks with independently controllable word lines. This segmentation enables selective erasure of only the intended block while protecting other blocks from erroneous erasure, thereby improving data accuracy without significantly increasing control mechanism complexity since each block has dedicated control lines.
Solution Approach 2:
The patent introduces control circuits and control lines as intermediaries between the external interface and memory cell transistors. These intermediaries enable precise control over which memory cells undergo erasure by routing appropriate voltages to specific word lines, thereby preventing erroneous data loss while maintaining a manageable control structure.
3Productivity
If selective data erasure is enabled, then data management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory cell array into multiple independently controllable blocks, each with its own word lines. This segmentation enables selective erasure of specific blocks, improving data management efficiency. The complexity increase is mitigated by using regular, repeating block structures that can be controlled through systematic addressing schemes.
Solution Approach 2:
The patent implements dynamic voltage control where different voltages are applied to different word lines based on the erasure requirements. This dynamic control enables selective erasure without requiring permanent structural modifications, allowing the device to adapt its erasure behavior flexibly while maintaining a relatively simple underlying device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables selective data erasure, preventing erroneous data loss and maintaining accurate threshold voltage distributions, thereby improving data management and operational reliability.
Implementation Method 1
A threshold voltage of the memory cell transistor is increased when a voltage that is applied to a word line connected to a gate thereof is lower than a voltage of a channel
Data Source
AI summary
A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.