Flash Memory Controller Data Grouping for Error Correction
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Solution Overview
Problem
As flash memory technology advances, ensuring effective and reliable error detection and correction becomes crucial due to increasing data storage demands, particularly in multi-level cell flash memory where data stability and reliability are compromised by power interruptions and semiconductor processing advancements.
Innovation Solution
A memory control method and apparatus that divides input data into data groups with fewer rows than data pages, using parity rows generated by methods like LDPC or BCH for error detection and correction, allowing dynamic adjustment of data group settings based on memory component reliability, thereby minimizing data loss and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written to multi-level cell flash memory with higher storage density, then storage capacity increases, but data stability and reliability deteriorate due to power interruptions and processing advancements
Solution Approach 1:
The patent segments data into multiple rows and divides these rows into groups, with each group associated with a parity row. This segmentation allows for granular error detection and correction at the row level while maintaining high storage density in multi-level cell flash memory.
Solution Approach 2:
The patent performs preliminary error correction by writing parity rows alongside data rows before actual storage operations. This preliminary action enables rapid error detection and correction during read operations, compensating for the reduced stability of multi-level cell memory.
2Ease of manufacture
If traditional error correction methods are used in multi-level cell flash memory, then implementation is simpler, but error correction capability is insufficient for the higher error rates in multi-level cell memory
Solution Approach 1:
The patent segments data into multiple rows and organizes them into groups with associated parity rows. This segmentation enables efficient error correction by limiting the correction scope to individual rows or small groups, making advanced error correction feasible while maintaining reasonable implementation complexity.
Solution Approach 2:
The patent introduces parity rows as intermediary elements that mediate between data rows and error correction mechanisms. These parity rows serve as intermediaries for detecting and correcting errors without requiring complex real-time computation, thus maintaining ease of implementation while improving error correction capability.
3Reliability
If more parity data is stored to improve error correction, then data reliability increases, but storage efficiency decreases
Solution Approach 1:
The patent applies local quality by associating parity rows with specific groups of data rows rather than using uniform error correction across all data. This allows for optimized parity allocation where each parity row protects only the necessary data rows, improving storage efficiency while maintaining reliability.
Solution Approach 2:
The patent enables dynamic adjustment of data group sizes and parity row allocations based on memory component reliability characteristics. By changing these parameters adaptively, the system optimizes the balance between error correction capability and storage efficiency for multi-level cell flash memory.
Data Source
AI summary
A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.