Write-in-Place Memory Page Erase and Selective Programming
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Solution Overview
Problem
Flash memory devices face long write latency due to the mismatch between the small program unit (e.g., one page of 256 Bytes) and the larger erase unit (e.g., one block of 4K Bytes), requiring a lengthy erase time before programming can occur.
Innovation Solution
A method for performing a Write-in-Place operation in a memory device, where only one page is erased and programmed, utilizing specific voltage biases to differentiate between cells to be programmed and erased, thereby eliminating the need to erase an entire block and improving write latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block is erased before programming a page, then all cells in the block are ensured to be in erase state, but the erase time is very long (25 milliseconds) which affects write latency
Solution Approach 1:
The patent divides the erase operation from the block level to the page level. Instead of erasing the entire block containing multiple pages, only the specific page that needs to be programmed is erased. This segmentation allows the system to erase only the necessary 256 bytes of a page rather than the entire 4K byte block, significantly reducing erase time and improving write latency while maintaining reliability of the programming operation.
2Loss of time
If only one page is erased instead of a block, then write latency is greatly improved, but differentiation between cells to be programmed and cells to be erased becomes more complex
Solution Approach 1:
The patent applies local quality by using different program biases for different cells within the same page. Cells that need to be programmed receive a first program bias, while cells that should remain erased receive a second program bias that is lower than the first. This localized differentiation allows selective programming within the erased page without affecting other cells, managing the complexity through precise local control rather than global operations.
Solution Approach 2:
The patent changes the voltage parameter (program bias) to differentiate between programming and non-programming operations. By adjusting the program bias voltage level, the system can selectively program only the intended cells while leaving other cells in the erased state. This parameter change approach simplifies the control logic compared to physical separation methods, as it uses voltage level discrimination to achieve selective cell programming.
Data Source
AI summary
A method for performing an operation in a memory device is provided. The method includes the following steps. An erasing operation is performed on one selected word line of the memory device to ensure that a plurality of first cells to be programed and a plurality of second cells to be erased connected to the selected word line have threshold voltages lower than a first predetermined level. A programming operation is performed on the selected word line, such that the first cells are suffered a first program bias and the second cells are suffered a second program bias which is lower than the first program bias.