Flash Memory Fail-Safe Erase Status Tracking
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Solution Overview
Problem
Flash memory devices face issues with incomplete erase operations due to power disconnections or shutdowns, leading to unpredictable results and potential data corruption when reading from partially erased blocks, necessitating a fail-safe erase mechanism to ensure data integrity.
Innovation Solution
A method and device for flash memory units that store erase status information in nonvolatile memory, allowing the controller to track pending erase operations and update status flags, ensuring that incompletely erased units are identified and scheduled for completion, thereby preventing data corruption and maintaining data integrity without modifying host software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operations are scheduled for later execution to reduce immediate processing time, then productivity is improved, but reliability deteriorates due to power disconnections leaving blocks in incomplete erase states
Solution Approach 1:
The patent applies preliminary action by setting erase status flags in nonvolatile memory before the actual erase operation begins. This allows the system to record the intent to erase data even before the erase process completes, ensuring that if power is lost, the controller can detect the pending erase state and complete the operation later, thus maintaining reliability while allowing flexible scheduling for productivity.
Solution Approach 2:
The patent implements feedback through erase status flags that provide continuous information about the erase state of memory blocks. The controller reads these flags to determine whether blocks have been completely erased before allowing new programming operations, creating a feedback loop that ensures data integrity without requiring constant monitoring of the erase process itself.
2Reliability
If erase status information is stored in nonvolatile memory to track pending operations, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into distinct functional sections: data storage blocks and separate erase status flag storage areas. This segmentation allows the status information to be stored in a dedicated, simple structure within the nonvolatile memory, reducing the complexity burden by organizing the device into modular, independent sections with clear responsibilities.
Solution Approach 2:
The erase status flags act as an intermediary between the physical erase operation and the controller's decision-making process. Rather than requiring the controller to directly monitor complex erase states or implement sophisticated tracking mechanisms, the simple binary flags serve as intermediaries that convey essential status information, thereby reducing device complexity while maintaining reliability.
3Productivity
If read operations are performed on partially erased blocks, then productivity is maintained, but harmful factors increase due to retrieval of random unstable data
Solution Approach 1:
The patent applies preliminary action by checking the erase status flags before allowing read operations on memory blocks. This preliminary check prevents reading from blocks that are in an incomplete erase state, thereby avoiding the generation of harmful unstable data while maintaining productivity by only permitting reads on fully erased or fully programmed blocks where data integrity is guaranteed.
Solution Approach 2:
The patent implements preliminary anti-action by proactively preventing read operations on blocks with pending erase status. Rather than allowing unstable data to be retrieved and then dealing with the consequences, the system takes preliminary action to block access to potentially corrupted data, thereby neutralizing the harmful effect before it can impact the application.
Data Source
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AI summary
The present disclosure provides a flash memory device including a flash memory comprising a plurality of nonvolatile memory cells, divided into a plurality of erase units; a memory section dedicated to storing erase status information, the erase status information indicating an erase status of the plurality of erase units; and a memory controller configured to receive an erase request indicating at least one erase unit; store erase status information for the at least one erase unit in the memory section; perform an erase operation on the at least one erase unit; and update the stored erase status information upon completion of the erase operation. In addition, the present disclosure provides a way how incomplete erase commands can be handled transparently in a fail safe way.