Flash Memory Non-Bijective Mapping for Reliability
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Solution Overview
Problem
Multi-bit-per-cell flash memory systems face a tradeoff between cost, reliability, and performance due to the negative effects of increasing the number of voltage levels, which decreases data retention and program/erase cycles while slowing read/write throughput.
Innovation Solution
A flash controller using a combination of an Error Correction Code (ECC) and a low-dimensional non-bijective mapping allows for optimal tradeoff among cost, reliability, and performance by using any number of states or voltage levels, not necessarily a power of 2, and inducing unequal probabilities over programmed states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of voltage levels or states programmed in a flash cell is increased, then the information bits per cell (IBPC) increases, but the data retention time decreases and the program/erase cycles decrease, resulting in lower reliability
Solution Approach 1:
The patent applies parameter changes by transitioning from a bijective mapping (one-to-one correspondence between information bits and voltage levels) to a non-bijective mapping where multiple information bit patterns can map to the same voltage level. This changes the mapping parameter to allow using a smaller number of voltage levels (e.g., 3 levels instead of 4), which directly improves data retention time and reliability while maintaining acceptable information storage capacity through the non-bijective mapping approach
2Quantity of substance
If the number of voltage levels or states programmed in a flash cell is increased, then the information bits per cell (IBPC) increases, but the read/write throughput decreases, resulting in slower performance
Solution Approach 1:
The patent changes the mapping parameter from bijective to non-bijective, enabling the use of fewer voltage levels (e.g., 3 levels instead of 4). This parameter change reduces the complexity of voltage level discrimination during read operations, thereby improving read/write throughput while maintaining the ability to store multiple information bits per cell through the non-bijective mapping strategy
3Ease of manufacture
If a bijective mapping is used to map information bits to voltage levels, then the implementation is simple, but the number of usable voltage levels is limited to powers of 2, reducing cost efficiency
Solution Approach 1:
The patent inverts the conventional approach by using a non-bijective mapping instead of a bijective mapping. This allows the system to use a smaller number of voltage levels (not necessarily a power of 2) while still achieving efficient information storage. The inversion of the mapping approach enables cost efficiency by reducing the number of voltage levels needed, and the patent provides methods to handle the increased complexity through systematic approaches to encoding and decoding
Data Source
AI summary
To store input data in a plurality of memory cells, a mapping function of bit sequences to physical parameter states of the cells is provided. The cells are programmed, in accordance with the mapping function, to store the input data, in a way that would store uniformly distributed data with a programming state distribution other than any native state distribution of the mapping function. To store input data in a single memory cell, a mapping function of bit sequences to states of a physical parameter of the cell, such that if uniformly distributed data were stored in a plurality of such memory cells then the states of the physical parameter of the cells would be distributed non-uniformly, is provided. The memory cell is programmed to store the input data in accordance with the mapping function.