3D NAND Memory Cell Erasing to Reduce Program Disturbance
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Solution Overview
Problem
High-density memory cells in semiconductor devices experience program disturbance due to coupling between memory cells, leading to unintentional programming of unselected cells.
Innovation Solution
A 3-dimensional NAND Flash memory device with top and dummy memory cells, controlled by a controller, uses specific voltage configurations and erasing methods to verify and reset these cells, reducing program disturbance by suppressing gate-induced drain leakage and capacitive coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density memory cells are incorporated to reduce device size and increase storage capability, then integration density is improved, but coupling between memory cells increases causing program disturbance
Solution Approach 1:
The memory device is divided into distinct segments including dummy memory cells separate from main memory cells, with separate control mechanisms. The dummy memory cells are segmented into first and second dummy memory cells with different control line configurations, allowing independent verification and resetting to prevent program disturbance in main memory cells
Solution Approach 2:
Dummy memory cells serve as intermediary elements between control lines and main memory cells. These dummy cells absorb excess coupling effects and allow verification of control line voltages before actual programming operations, preventing unintended programming of main memory cells
2Reliability
If verification and resetting of dummy memory cells is performed before erasing main memory cells, then program disturbance is reduced, but erasing time is increased
Solution Approach 1:
Verification and resetting of dummy memory cells is performed as a preliminary action before the actual erasing of main memory cells. This preliminary verification ensures control lines are properly configured, preventing program disturbance during subsequent programming operations while maintaining efficient erasing throughput
Solution Approach 2:
The dummy memory cells perform self-verification and self-resetting functions that automatically prepare the system for main memory cell erasing. This self-service mechanism reduces the need for complex external control and minimizes the time overhead of verification procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces program disturbance by ensuring proper threshold voltages and reducing unintended programming, enhancing device performance and reliability.
Implementation Method 1
reducing program disturbance by suppressing gate-induced drain leakage and capacitive coupling effects
Implementation Method 2
reducing program disturbance by suppressing gate-induced drain leakage and capacitive coupling effects
Data Source
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AI summary
An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.