Read-Only Memories TRIZ Cases

A Multiple Shallow Threshold expert equalizer targets NAND read noise with localized models that reduce latency and memory demands.

This semiconductor memory circuit copies unit structures to assess parasitics and improve time-divisional OTP write reliability.

Memristor cells store weights and perform non-binary neural computation in memory.

Upper wirings prevent diffusion depletion during high-voltage flash-memory transfer.

This case uses closed-ended semiconductor channels around word lines to isolate memory levels, improve gate control, and reduce leakage.

During programming, page buffers selectively fix or change bit-line voltage to remove trapped charge and improve memory reliability.

This case uses impact-ionization holes and page refresh to stabilize floating-body potential for accurate memory reads and writes.

Page buffers use higher and lower precharge voltages across read phases to limit channel-voltage fluctuation in dense memory.

Alternating or patterned read-voltage polarity helps stabilize the read window and lower bit error rates in polarity-written memory cells.

Algorithm qualifier commands adjust memory trim settings to preserve data retention.

During multi-pass sensing, grouped memory states lock out selected bit lines with near-zero voltage to conserve current.

Relocating selection transistors to the array periphery reduces chip area, improves layout uniformity, and cuts control signals.

A recessed alignment vertical channel in the step key preserves mold shape and improves photolithographic accuracy in stacked memory.

Separate tests for full blocks and sub-blocks improve erase efficiency while enabling defect detection and valid-data transfer.

Separate command/address and data paths use clock timing to sustain efficient transfer as memory I/O speeds increase.

The controller compares ON-cell counts across read voltages to locate a threshold minimum and reduce erroneous memory reads.

A peripheral circuit uses identification information and the first programmed state to restore the intended second state after power loss.

This memory architecture shares high-voltage operation between cell and selection transistors to reduce FinFET MTPM cell size.

Target-dependent ISPP step voltages streamline coarse programming while reducing coupling effects, threshold shifts, and operation time.

This case uses selective conductive-material filling and etching to vary gate-line thickness across stacked memory-cell tiers.

This FeRAM case adjusts digit-line and plate-line voltages to program both logic states and meet tighter DRAM tRP timing.

A verify-driven erase voltage adjusts pulses by cell count, improving erase accuracy while reducing time and cell stress.

Phase-divided internal strobe signals enable fast memory transfer with less power.

This 3D NAND approach verifies and resets failed dummy cells before erasing main cells, limiting coupling-driven program disturbance.

An artificial neural network infers cell voltages from chip and physical data to improve consistency across stacked V-NAND word lines.

A segmented, multi-level ROM encoding approach preserves address fault detection while reducing encoder complexity, switches, and die space.

This case groups non-volatile memory cells, screens read variance, and deeply programs noisier cells to stabilize reads.

Version-specific programs let old and new storage controllers maintain I/O continuity during staged hardware and software upgrades.

This case uses same-polarity current pulses to program different data states concurrently within a tile, cutting time and energy use.

This case separates stacked transistor and wiring levels, using power delivery and heat spreading to support dense connections.

Non-volatile memory arrays combine synapse storage and computation, while split banks improve scalability, access, and energy efficiency.

A paired-cell programming scheme excludes two state combinations, reducing bipolar sense power while preserving data storage.

Separate memory blocks and paired search cells improve in-memory search density, data length, and power efficiency.

Encoded data and switching-event feedback set reference voltage for reliable reads across variable memory-cell characteristics.

After 3D NAND reads, staged wordline grounding discharges trapped charge, limiting Vt shifts and read window budget degradation.

This case shows how segmented latch, hookup, and pre-charge regions streamline sense amplifier paths for faster NAND memory transfer.

This memory programming case uses stepped source-line and bit-line voltages to balance channel potential against hot carrier disturbance.

Separate verify voltages and selective reprogramming counter coupling-driven threshold shifts in highly integrated 3D memory cells.

Wordline-specific voltage compensation lowers re-read triggers and latency when reading partially programmed non-volatile blocks.

Isolate and reset faulty memory chips without disrupting normal operation.

Different bit-line voltages compensate for slit-related threshold and speed differences, improving read consistency across memory cells.

This case uses dielectric breakdown in a 1T1C MIM capacitor to address memory-cell area, voltage, and reliability constraints.

This case uses insulating barriers between 3D NAND charge layers to limit migration and reduce data retention failures.

This case applies vertical stacking, GAA cells, and shared bit/source lines to raise memory density while limiting interconnect burden.

Logical address patterns isolate defective word lines, reclaim usable blocks, and reduce read-only mode risk in flash storage.

A multi-latch page buffer segments 5-bit data across memory cells, using inversion patterns to reduce latch count and conserve area.

Independent source-line drivers handle cell subsets, distributing read current to improve margins and reduce driver damage risk.

This memory architecture uses dual gate conductors and controlled hole retention to reduce coupling noise and improve read/write margins.

This I/O case replaces full data-eye construction with duty-cycle feedback to converge on an accurate reference voltage faster.

Separate memory cell arrays combine three threshold levels, increasing storage density while keeping read and write operations manageable.