Semiconductor OTP Memory Circuit with Dummy Units for Parasitic Evaluation
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Solution Overview
Problem
Existing semiconductor devices with OTP memory lack effective means to evaluate circuit configurations, particularly parasitic components, which affects the reliability and efficiency of information write and read operations.
Innovation Solution
A semiconductor device design featuring a plurality of units with a memory element and transistors arranged between terminals, allowing for time-divisional write operations and parasitic resistance evaluation, along with ESD protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory element is arranged between terminals with transistors for write operations, then information storage capability is improved, but parasitic components in the circuit affect the reliability of write and read operations
Solution Approach 1:
The patent creates a dummy unit that copies the circuit configuration of the memory unit, including the same number and arrangement of transistors and interconnect structures. This dummy unit serves as a reference for evaluating parasitic components, allowing the system to measure and compensate for parasitic effects without adding functional complexity to the actual memory operation.
Solution Approach 2:
The patent introduces a dummy unit as an intermediary structure that mediates between the memory unit and the evaluation requirements. This dummy unit acts as a test vehicle that isolates parasitic component measurement from actual memory operations, enabling separate evaluation and compensation of parasitic effects.
2Measurement precision
If multiple units are arrayed in a predetermined direction with corresponding transistors, then evaluation of circuit configuration becomes possible, but device structure becomes more complex
Solution Approach 1:
The patent segments the device into functional memory units and evaluation dummy units arranged in the same predetermined direction. Each unit is independently structured with its own transistors and interconnects, allowing separate evaluation of parasitic components while maintaining the overall arrayed structure. This segmentation enables precise measurement without requiring a completely different device architecture.
3Reliability
If time-divisional write operations are implemented, then write reliability is improved, but operation time increases
Solution Approach 1:
The patent implements time-divisional write operations where different units are written to in sequential time slots. The dummy unit is evaluated during periods when memory units are being written, and vice versa. This periodic alternation between evaluation and write operations allows both functions to occur without overlapping, ensuring write reliability through proper timing while managing the total operation time through efficient scheduling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of write operations and protects against electrostatic discharge, improving the capacity and efficiency of memory elements.
Implementation Method 1
utilizing DMOS transistors and anti-fuse elements for dielectric breakdown-based writing
Data Source
AI summary
A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit.