Semiconductor Memory Adaptive Erase Voltage Control for Shorter Erase Time
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Solution Overview
Problem
Existing NAND flash memory technologies face challenges in achieving shorter erase times and higher erase verify accuracy while minimizing stress on memory cells, as they often require multiple erase pulses and have varying erase characteristics due to differing data retention characteristics.
Innovation Solution
A semiconductor memory device that controls the potentials of word lines and bit lines using a control circuit to erase multiple memory cells simultaneously, performs verify operations at different levels, and adjusts erase voltages based on the number of cells exceeding a verify level to optimize erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase voltage is made lower to erase memory cells shallowly, then the data retention characteristic is improved, but the erase time increases and multiple erase pulses are required
Solution Approach 1:
The patent segments the memory cell array into multiple blocks, allowing selective erasure of only those blocks containing invalid data rather than erasing the entire array. This segmentation enables the system to achieve complete erasure of valid data while minimizing the number of erase pulses applied, thus reducing both erase time and stress on memory cells.
Solution Approach 2:
The patent applies partial erasure action by identifying and erasing only the specific blocks that contain invalid data, rather than performing a full array erasure. This partial action approach reduces the total number of erase pulses required while ensuring that all valid data is properly erased, balancing data retention with erase efficiency.
2Reliability
If the erase voltage is stepped up gradually to prevent excessive erasure, then the stress on cells is reduced, but the erase time increases
Solution Approach 1:
The patent performs preliminary identification of invalid data blocks before initiating the erasure process. By using metadata or file system information to locate blocks containing invalid data, the system can prepare a targeted erasure list, allowing subsequent erasure operations to be performed efficiently with minimal pulses while avoiding unnecessary erasure of already-valid blocks.
Solution Approach 2:
The patent changes the parameter of erase operation scope from full-array to selective-block erasure. By dynamically adjusting which blocks are subjected to erasure based on their validity status, the system reduces the cumulative stress on memory cells while maintaining effective erasure of valid data, thereby reducing both time and stress parameters simultaneously.
3Reliability
If multiple erase pulses are applied to ensure complete erasure, then the erasure reliability is improved, but the erase time increases and cell deterioration accelerates
Solution Approach 1:
The patent segments the erasure operation into block-level units, allowing independent verification and erasure of each block. This segmentation enables the system to apply erasure pulses only to blocks that require it, reducing the cumulative number of pulses applied to individual cells and thereby extending cell lifespan while maintaining complete erasure reliability for blocks that need it.
Solution Approach 2:
The patent implements feedback mechanisms through metadata tracking and verification operations that monitor the erasure status of each block. This feedback allows the system to determine when erasure is complete for each block and stop applying pulses accordingly, preventing unnecessary repeated erasure cycles that would accelerate cell deterioration while ensuring complete erasure where needed.
Data Source
AI summary
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.