3D NAND Charge Storage Layers for Stable Data Retention
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Solution Overview
Problem
Three-dimensional NAND flash memories face challenges with charge retention properties, leading to data retention failures due to charge movement between adjacent memory cells.
Innovation Solution
The semiconductor storage device incorporates a design with physically separated charge storage layers and specific atomic ratios of silicon to nitrogen in these layers, along with additional insulating layers to prevent charge movement, enhancing charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage layers are placed adjacent to each other in three-dimensional NAND flash memory, then integration density is improved, but charge retention property deteriorates due to charge movement between adjacent memory cells
Solution Approach 1:
The charge storage layer is divided into multiple sub-layers (first charge storage layer and second charge storage layer) with an insulating layer positioned between them. This segmentation physically separates the charge storage regions, preventing charge movement between adjacent memory cells while maintaining high integration density through the vertical stacking configuration.
Solution Approach 2:
An insulating layer is introduced as an intermediary between adjacent charge storage layers. This intermediate layer acts as a barrier that prevents charge migration between neighboring memory cells, thereby improving charge retention property without compromising the integrated three-dimensional structure.
2Reliability
If insulating layers are added between charge storage layers to prevent charge movement, then charge retention property is improved, but device complexity increases
Solution Approach 1:
The insulating layer positioned between charge storage layers serves multiple functions simultaneously: it acts as a charge blocking barrier to prevent charge movement, provides electrical isolation between adjacent memory cells, and maintains the structural integrity of the vertical stack. This multi-functionality improves charge retention without proportionally increasing device complexity.
Solution Approach 2:
The insulating layer is nested within the vertical stack structure, positioned between the first and second charge storage layers. This nested configuration integrates the isolation function within the existing memory cell architecture, minimizing additional complexity while achieving improved charge retention through the layered arrangement.
Data Source
AI summary
A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.