Split Analog Neural Memory Arrays for Efficient In-Situ Computing
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Solution Overview
Problem
The development of high-performance artificial neural networks is hindered by a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability, as existing digital systems are costly and inefficient compared to biological networks, and CMOS-implemented synapses are too bulky for practical neural networks.
Innovation Solution
The use of non-volatile memory arrays as synapses in artificial neural networks, configured for individual programming and continuous analog programming, allowing precise tuning of memory cells to store synapse weights, and splitting the array into multiple parts with dedicated and shared circuitry to enhance efficiency and reduce space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but cost and energy efficiency deteriorate
Solution Approach 1:
The patent replaces digital computational systems (supercomputers, GPUs) with an analog neuromorphic memory system that performs computational functions through physical memory operations. The memory array directly implements neural network computations using analog voltage signals, eliminating the need for digital processing hardware and achieving both high parallelism and energy efficiency simultaneously.
Solution Approach 2:
The memory array serves multiple functions: it stores synapse weights, performs multiplication operations, and enables parallel computation across all synapses simultaneously. This multi-functional approach allows a single hardware component to replace both storage and processing functions that would otherwise require separate digital systems.
2Use of energy by moving object
If CMOS analog circuits are used for artificial neural networks, then energy efficiency is improved, but device area increases due to bulky synapse implementations
Solution Approach 1:
The patent merges the synapse weight storage function and the multiplication computation function into a single memory cell. The memory array simultaneously stores synapse weights and performs the multiplication operation with input signals, eliminating the need for separate analog circuitry and dramatically reducing device area while maintaining energy efficiency.
Solution Approach 2:
The patent uses standard CMOS memory cell designs that can be densely replicated to form large-scale neural networks. By utilizing proven memory cell architectures rather than custom analog circuits, the system achieves compact scaling while maintaining the energy efficiency benefits of analog computation.
3Productivity
If a single large memory array is used for neural network computations, then computational capacity is improved, but access time and control complexity increase
Solution Approach 1:
The patent divides the memory array into multiple independently accessible banks or segments. Each bank can be accessed simultaneously through dedicated word lines and bit lines, enabling parallel data retrieval and reducing overall access time while maintaining high computational capacity through the combined capacity of all segments.
Solution Approach 2:
The patent organizes the memory array in a two-dimensional crossbar architecture with row and column addressing. This spatial organization allows simultaneous access to multiple memory locations through different word lines and bit lines, effectively adding temporal parallelism to the computational capacity without increasing access time proportionally.
Data Source
AI summary
Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.