Flash Memory Transfer Transistors Preventing Diffusion Depletion
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Solution Overview
Problem
Conventional NAND cell type flash memory transfer transistors fail to transfer sufficient high voltage, leading to malfunctions and inadequate multi-level cell operations due to depletion of diffusion layers.
Innovation Solution
The implementation of transfer transistors with upper layer wirings short-circuited to the gate electrode, preventing depletion of diffusion layers and ensuring successful high voltage transfer by maintaining a predetermined voltage on these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transfer transistors with high breakdown voltage are used to transfer high voltage to memory cells, then the voltage transfer capability is improved, but the diffusion layers become depleted leading to malfunction
Solution Approach 1:
The patent applies local quality by providing different voltage conditions to different regions of the transfer transistor. Specifically, upper layer wirings are connected to diffusion layers to maintain a predetermined voltage (such as ground potential) in those specific regions, while allowing other regions to operate with high voltage for data transfer. This localized voltage control prevents depletion in critical areas while maintaining high voltage transfer capability where needed.
Solution Approach 2:
The upper layer wirings act as intermediary elements between the high voltage transfer transistor and the diffusion layers. These wirings serve as a mediator that maintains a stable predetermined voltage on the diffusion layers, preventing direct depletion effects while allowing the transistor to function with high breakdown voltage for effective data transfer operations.
2Adaptability or versatility
If high voltage is transferred to control gate lines for multi-level cell operations, then data storage capability is improved, but transfer transistor malfunction occurs due to insufficient voltage transfer
Solution Approach 1:
The patent implements local quality by applying different voltage conditions to different parts of the transfer transistor system. The upper layer wirings maintain a predetermined voltage locally at the diffusion layers, enabling the transistor to handle high voltage for multi-level cell operations without experiencing depletion-induced malfunction in critical regions.
Data Source
AI summary
A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.