Anti-Fuse Array Peripheral Selection for Compact Chip Layout
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Solution Overview
Problem
Current anti-fuse array structures occupy a large chip area and exhibit poor uniformity, hindering miniaturization and high integration levels due to the need for selection transistors that occupy significant space.
Innovation Solution
The selection circuit area with multiple selection transistors is arranged on the periphery of the anti-fuse array area, reducing the array's length and width, enhancing layout uniformity, and allowing for fewer control signals, with shared electrodes for improved space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selection transistors are integrated within the anti-fuse array structure, then the array can be programmed and read, but the chip area occupied increases significantly
Solution Approach 1:
The selection transistors are extracted from the anti-fuse array structure and placed in the periphery region. This separation removes the space-consuming transistors from the array core, allowing the anti-fuse cells to be densely packed without interspersed transistor structures, thereby reducing the overall chip area while preserving programming and reading capabilities through the external selection circuit.
Solution Approach 2:
The selection transistors are relocated from the two-dimensional plane of the array to the periphery region, effectively utilizing the outer boundary space. This dimensional reorganization allows the array area to be minimized while the selection functionality is maintained in the surrounding region, optimizing the overall layout efficiency.
2Area of stationary object
If selection transistors are placed in the periphery, then the array area is minimized, but the layout uniformity deteriorates
Solution Approach 1:
The chip is segmented into distinct functional regions: the anti-fuse array area in the center and the selection circuit area in the periphery. This segmentation allows each region to be optimized independently - the array achieves maximum density and uniformity, while the periphery accommodates the selection transistors, resulting in an overall balanced and uniform layout.
3Measurement precision
If more control signals are used for selection transistors, then precise cell selection is achieved, but the number of control signals increases
Solution Approach 1:
The selection transistors in the periphery are designed to handle multiple selection functions using a reduced set of control signals. By strategically placing these multi-functional transistors, the circuit achieves precise cell selection capability while minimizing the number of required control signals, thus reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes the anti-fuse array's area, improves uniformity, and increases integration level while reducing the number of control signals, thus optimizing chip layout and efficiency.
Implementation Method 1
When it is programmed (a high voltage is applied from external), the dielectric layer is broken down by high electric field, and an electrical connection is formed between the conductive layers on two sides
Data Source
AI summary
An anti-fuse array structure, an operation method thereof and a memory are provided. The anti-fuse array structure includes an anti-fuse array area and a selection circuit area. The anti-fuse array area includes a plurality of anti-fuse cells, and the selection circuit area includes a plurality of selection transistors. The selection circuit area is located on at least one side of the anti-fuse array area.