Fast I/O Reference Voltage Training Using Duty-Cycle Feedback
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Solution Overview
Problem
Conventional methods for determining the optimal reference voltage in NAND flash I/O interfaces are time-consuming and prone to inaccuracies due to drift and noise, leading to inefficiencies and high power consumption.
Innovation Solution
A fast write training method that detects the optimal reference voltage based on the duty cycle and voltage swing of a periodic input signal, using a feedback loop to converge the generated voltage to the detected optimal value, reducing the time required for training to a single page write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional methods are used to determine optimal reference voltage through full data eye construction, then measurement accuracy can be achieved, but training time becomes excessively long and power consumption increases
Solution Approach 1:
The patent extracts only the essential characteristics needed for reference voltage detection by analyzing the duty cycle of the input signal at different voltage points, rather than constructing the complete data eye. This selective extraction of critical information (duty cycle variations) eliminates the time-consuming full data eye construction while still providing sufficient data to determine the optimal reference voltage point where duty cycle equals 50%.
Solution Approach 2:
Instead of performing the complete data eye construction process, the patent applies partial action by only measuring the duty cycle at specific voltage points during the training sequence. This partial measurement approach provides enough information to identify the optimal reference voltage without the overhead of full data eye construction, significantly reducing training time while maintaining adequate precision.
2Measurement precision
If conventional training methods are used, then comprehensive data analysis can be performed, but power consumption increases due to extended training duration
Solution Approach 1:
The patent extracts only the duty cycle information from the input signal during training, rather than performing comprehensive data eye construction and analysis. By focusing solely on duty cycle measurements at different voltage points, the system achieves reference voltage optimization with minimal power consumption, as duty cycle detection requires significantly less computational resources and time than full data eye analysis.
Solution Approach 2:
The patent applies partial action by performing only the essential duty cycle measurements needed for reference voltage detection, omitting the redundant steps of full data eye construction. This partial approach maintains sufficient measurement precision for optimization while dramatically reducing power consumption associated with extended training operations.
3Productivity
If fast training methods are used, then training time is reduced, but measurement accuracy may deteriorate due to drift and noise
Solution Approach 1:
The patent implements feedback by continuously monitoring the duty cycle of the input signal and using this information to adjust the reference voltage selection. The duty cycle measurements provide real-time feedback about the signal characteristics, allowing the system to identify the optimal reference voltage point (where duty cycle = 50%) even in the presence of drift and noise, maintaining measurement accuracy while achieving fast training.
4Reliability
If Center-Tap Termination is implemented to handle large load capacitance, then I/O interface performance can be maintained, but power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by implementing adaptive On-Die Termination (ODT) that can be dynamically adjusted based on the detected optimal reference voltage and signal characteristics. Unlike fixed Center-Tap Termination, the dynamic ODT allows the system to optimize termination settings for different operating conditions, achieving reliable I/O interface performance while consuming significantly less power by activating termination only when and where needed.
Data Source
AI summary
Systems and methods disclosed herein provide for fast write training that be performed to identify an optimal reference voltage for distinguishing between logic levels of an input signal. An example of the systems and methods disclosed herein include receiving a clock signal at an input-output pad of a receiving device and detecting a voltage level of the clock signal based on a duty cycle and voltage swing of the clock signal. A voltage generator circuit is trained to generate a calibrated reference voltage according to the detected voltage level, and the calibrated reference voltage is supplied to an input receiver of the receiving device from the voltage generator circuit.


