Stacked Memory Cell Arrays with Variable Gate-Line Thickness
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Solution Overview
Problem
Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with optimal conductive gate line conductivity and reduced lateral space between memory cells, leading to increased resistance.
Innovation Solution
The method involves forming a stack with alternating tiers of different vertical thicknesses, where conductive material is selectively filled and etched to optimize conductive gate lines, reducing resistance by varying the thickness of conductive tiers and ensuring direct electrical coupling with channel material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform thickness conductive tiers are used in vertically-stacked memory cells, then manufacturing is simpler, but resistance increases due to insufficient optimization of conductive gate lines
Solution Approach 1:
The patent applies local quality by varying the thickness of conductive tiers at different vertical positions within the stack. Specifically, intermediate conductive tiers have different thicknesses compared to top and bottom tiers, optimizing electrical conductivity where needed while maintaining manufacturability. This localized variation in thickness allows tailored electrical properties in different regions of the memory structure without requiring complete redesign of the entire stack.
2Productivity
If larger lateral space is provided between memory cells, then manufacturing is easier, but device density decreases
Solution Approach 1:
The patent employs parameter changes by systematically varying the thickness parameter of conductive tiers throughout the stack. By adjusting thickness values of different conductive tiers (thinner at top and bottom, thicker in intermediate positions), the invention optimizes both electrical performance and spatial utilization. This parameter optimization enables reduced lateral spacing between memory cells while maintaining adequate conductivity, thereby increasing device density without compromising manufacturability.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.