Nonvolatile Memory Blocks with Sub-Block Defect Detection
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Solution Overview
Problem
Nonvolatile memory devices face inefficiencies in erase operations due to increased block sizes, which can lead to channel hole burst defects, necessitating improved methods to retain valid data and enhance reliability.
Innovation Solution
The implementation of a memory cell array with sub-block divisions and distinct defect detection tests for full and sub-blocks, utilizing different test conditions to identify and manage defects effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stages of the nonvolatile memory device is increased, then the storage capacity is improved, but the block size increases and erase operation efficiency deteriorates
Solution Approach 1:
The block is divided into several sub blocks so that data may be erased in units of sub blocks, whereby the efficiency of the erase operation may be increased. This segmentation allows selective erasing of only the necessary portions rather than entire large blocks, directly resolving the efficiency problem while maintaining high storage capacity through increased staging.
2Quantity of substance
If the block size is increased, then the storage capacity is improved, but the minimum erase unit size increases and erase operation efficiency deteriorates
Solution Approach 1:
The block is divided into several sub blocks so that data may be erased in units of sub blocks, whereby the efficiency of the erase operation may be increased. This allows the system to erase only the necessary sub blocks rather than entire large blocks, reducing erase operation time while maintaining large block sizes for high storage capacity.
3Productivity
If the block is divided into sub blocks, then the erase operation efficiency is improved, but the device complexity increases
Solution Approach 1:
The block is divided into several sub blocks so that data may be erased in units of sub blocks, whereby the efficiency of the erase operation may be increased. The control logic is configured to manage this segmentation, performing different tests for full blocks versus sub blocks to detect defects and transfer valid data appropriately.
Solution Approach 2:
The control logic is designed to handle both full blocks and sub blocks using a unified defect detection and data transfer mechanism. The same control logic performs different tests depending on whether the block is full or divided, providing a multi-functional solution that manages complexity internally while presenting a simplified interface.
4Reliability
If a defect detection test is performed on the block, then the reliability is improved, but the additional operation time increases
Solution Approach 1:
Different tests are performed depending on the block type: a first test is performed for full blocks and a second test is performed for sub blocks. This partial action approach performs only the necessary testing for each block type rather than applying a uniform comprehensive test to all blocks, reducing overall test time while maintaining reliability through appropriate defect detection.
Data Source
AI summary
A nonvolatile memory device comprising a memory cell array including a first block including a first sub block having a first plurality of memory cells and a second sub block having a second plurality of memory cells, and a second block including a third plurality of memory cells and being a full block that is not divided into sub blocks. The nonvolatile memory device further comprising a control logic configured to write, read, and erase data to and from the memory cell array. The control logic further configured to perform a first test to detect a defect of the second block in response to a first erase command for the second block, and performs a second test different from the first test to detect a defect of the first sub block in response to a second erase command for the first sub block.