Semiconductor Memory Read-Voltage Search for Accurate Data Reads
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Solution Overview
Problem
Existing memory systems face challenges in accurately determining the local minimum point in threshold voltage distributions of semiconductor memory cells, leading to erroneous data reading due to overlapping threshold voltage lobes, especially when using default read voltages that may misjudge the actual state of memory cell transistors.
Innovation Solution
A memory controller employs a method to search for and estimate the local minimum point by executing multiple read operations with varying read voltages, analyzing ON-cell counts, and adjusting the search direction based on differences and expected values to precisely determine the appropriate read voltage for accurate data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If default read voltages are used for reading data, then the read operation is simple and fast, but the data reading accuracy deteriorates due to overlapping threshold voltage lobes
Solution Approach 1:
The patent applies preliminary action by performing a search for the local minimum point before the actual data reading operation. The memory controller executes preliminary read operations at different voltages to identify the local minimum point of the threshold voltage distribution, then uses this information to adjust the read voltage for accurate data retrieval. This preliminary search resolves the contradiction by preparing the optimal read voltage in advance, ensuring both accuracy and efficiency in the subsequent read operation.
2Measurement precision
If multiple read operations with varying voltages are performed to search for local minimum point, then data reading accuracy is improved, but the time required for read operation increases
Solution Approach 1:
The patent applies partial action by performing read operations at a limited number of discrete voltage levels (e.g., three specific voltages) rather than continuously scanning the entire voltage range. The memory controller compares ON-cell counts from these partial measurements to determine the search direction and estimate the local minimum point. This approach achieves sufficient accuracy for identifying the local minimum while significantly reducing the time required compared to exhaustive search methods.
3Measurement precision
If the search for local minimum point is performed exhaustively, then the accuracy of determining the local minimum point is improved, but the complexity of the control process increases
Solution Approach 1:
The patent applies segmentation by dividing the search process into distinct stages: initial read operations at different voltages, comparison of ON-cell counts, determination of search direction, and iterative refinement. The control process is segmented into discrete decision steps based on comparing measured values with expected values, which simplifies the overall control logic while maintaining high accuracy in local minimum point determination.
4Reliability
If default read voltage is used, then the read operation is fast, but erroneous data reading occurs due to misjudging the actual state of memory cell transistors
Solution Approach 1:
The patent applies feedback by using the measured ON-cell counts from preliminary read operations to adjust the read voltage for subsequent data retrieval. The memory controller compares the measured ON-cell counts with expected values and uses this feedback information to determine the search direction and estimate the local minimum point. This feedback mechanism ensures high data reading reliability by adapting the read voltage to the actual threshold voltage distribution, while the iterative nature of the feedback process efficiently converges to the optimal voltage without excessive time consumption.
Data Source
AI summary
A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.