Non-Volatile Memory Read Voltage Compensation for Partial Blocks

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Solution Overview

Problem

Existing memory devices experience high read latency and re-read triggers due to partially-programmed blocks, particularly in non-volatile memory, which are not effectively addressed by reactive re-read strategies.

Innovation Solution

Proactively adjusting read voltages for partially-programmed blocks in non-volatile memory devices, identifying vulnerable wordlines through a wordline-specific pattern, and applying a read offset voltage to reduce re-read triggers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reactive re-read strategies are used for partially-programmed blocks, then data retrieval is attempted, but read latency increases and re-read trigger rates remain high

Engineering Contradiction:

Improvedata retrieval accuracyVSAvoidread latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system proactively identifies partially-programmed blocks before read operations and applies voltage compensation in advance. By detecting blocks with incomplete programming states and pre-adjusting read voltages, the system prevents read failures before they occur, eliminating the need for reactive re-read operations and reducing read latency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts read voltages based on the programming state of memory blocks. By monitoring block status and adapting voltage levels in real-time according to whether blocks are fully or partially programmed, the system optimizes read operations for different block states, improving both reliability and speed.

Inventive Principle:

Principle #15Dynamics

2Productivity

If standard read voltage is applied to partially-programmed blocks, then read operations can be performed, but re-read trigger rates increase significantly

Engineering Contradiction:

Improveread operation throughputVSAvoidread success rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system applies different read voltage compensation strategies to different memory blocks based on their programming status. Fully-programmed blocks use standard read voltages, while partially-programmed blocks receive proactive voltage compensation. This localized approach optimizes read success rates for vulnerable blocks without affecting overall system throughput.

Inventive Principle:

Principle #3Local quality

3Loss of time

If proactive voltage adjustment is applied to all blocks, then read latency is reduced, but device complexity increases

Engineering Contradiction:

Improveread latencyVSAvoidvoltage control logic

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The system applies proactive voltage adjustment only to partially-programmed blocks rather than all blocks. By selectively identifying and treating only the vulnerable subset of blocks that require compensation, the system reduces read latency where needed while minimizing the complexity overhead of the voltage control logic.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12362016B2Read latency reduction for partially-programmed block of non-volatile memory

Publication Date: 2025.07.15 INTEL NDTM US LLC

AI summary

Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.