Semiconductor Memory De-Trap Control for Threshold Voltage Stability

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Solution Overview

Problem

Non-volatile memory devices face reliability issues due to deteriorating threshold voltage distribution of memory cells with increasing program and erase operations, necessitating improved methods to maintain data integrity.

Innovation Solution

A semiconductor device with a control circuit that performs a de-trap operation on memory cells during programming, selectively fixing or changing voltage levels based on program completion status to improve threshold voltage distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If program operations are performed repeatedly to increase storage capacity utilization, then data storage capability is improved, but threshold voltage distribution deteriorates and reliability decreases

Engineering Contradiction:
Improvestorage capacity utilizationVSAvoidthreshold voltage distribution
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The de-trap operation is performed in advance during the programming process (between program pulse application and verification) to prevent threshold voltage distribution deterioration before it occurs. This preliminary action removes trapped charges that would otherwise degrade memory cell reliability after repeated program operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful effect of trapped charges (which cause threshold voltage distribution deterioration) into a beneficial process by intentionally inducing controlled charge trapping during programming and then removing it through de-trap operations. This controlled cycle actually improves reliability by preventing uncontrolled charge accumulation.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If de-trap operation is performed on all memory cells, then threshold voltage distribution is improved, but operation complexity increases

Engineering Contradiction:
Improvethreshold voltage distributionVSAvoidoperation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The de-trap operation is applied selectively only to memory cells that require it, based on their individual programming status. The control circuit identifies which cells have incomplete program operations and applies de-trap only to those specific cells, rather than uniformly to all cells, thereby reducing unnecessary operations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system uses program verification results as feedback to determine whether de-trap operation is needed. The control circuit monitors the completion status of program operations and dynamically adjusts de-trap application accordingly, creating a closed-loop control system that optimizes operation complexity.

Inventive Principle:
Principle #23Feedback

3Reliability

If program verification is performed frequently to ensure data integrity, then reliability is improved, but operation time increases

Engineering Contradiction:
Improvedata integrityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The de-trap operation is performed preliminarily during the programming phase to prevent threshold voltage shifts that would require additional verification cycles. By addressing potential reliability issues early, the system reduces the need for repeated verification operations, thereby reducing total operation time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12374410B2Semiconductor device and operating method of semiconductor device
Publication Date: 2025.07.29 SK HYNIX INC
  • US12374410B2 patent drawing
  • US12374410B2 patent drawing
  • US12374410B2 patent drawing

AI summary

Disclosed is a semiconductor device including a plurality of strings connected between a plurality of bit lines and a source line, a plurality of page buffers connected to the plurality of bit lines, respectively, and configured to adjust a voltage level of each of the plurality of bit lines, and a control circuit configured to control the plurality of page buffers to fix a voltage level of a bit line connected to a string including a memory cell on which a program operation has been completely performed and to change a voltage level of a bit line connected to a string including a memory cell on which the program operation has not been completely performed, during a de-trap operation.