Non-Volatile Memory Interface Clocking for Efficient Command Transfer
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Solution Overview
Problem
Despite the increase in data input/output speed between non-volatile memory devices and controllers, the efficiency of command and address transmission remains reduced due to fixed timing parameters, leading to inefficiencies in data transfer.
Innovation Solution
Implementing a non-volatile memory device with a clock pin, input/output pins, and a command/address buffer that synchronizes commands, addresses, and data with a clock signal, allowing for separate channels for command/address transmission and data transfer, and utilizing control logic to manage memory cell operations based on buffered inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data input/output speed is increased, then data transmission rate is improved, but input/output efficiency is reduced due to fixed timing parameters
Solution Approach 1:
The patent introduces a clock signal that dynamically adjusts the timing of command and address transmission. Instead of fixed timing parameters, the system uses clock cycles to synchronize data transfer, allowing the timing to adapt to varying data speeds. The clock pin receives a clock signal from the controller, and the command/address buffer operates in synchronization with this clock signal, enabling flexible timing adjustment while maintaining high data throughput.
2Ease of operation
If fixed timing parameters are used for command and address transmission, then simplicity of control is maintained, but transmission efficiency is reduced at high data speeds
Solution Approach 1:
The patent changes the timing parameter from fixed time intervals to clock-synchronized intervals. The clock signal provides a dynamic timing reference that can be adjusted by changing the clock frequency, allowing the system to optimize transmission efficiency for different data speeds while maintaining a simple synchronous control mechanism. The command/address buffer uses the clock signal to determine when to latch and process commands and addresses, replacing fixed timing with flexible clock-based timing.
3Adaptability or versatility
If separate channels are implemented for command/address and data transfer, then functional clarity is improved, but device complexity is increased
Solution Approach 1:
The patent segments the input/output interface into separate functional channels: a first input/output pin for command and address transmission, and a second input/output pin for data transfer. This segmentation provides clear functional separation, allowing each channel to be optimized independently. The command/address buffer is specifically dedicated to processing commands and addresses from the first channel, while data operations use the second channel, improving functional clarity without requiring excessive complexity through modular design.
Data Source
AI summary
A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.