Page Buffer Latch Encoding for Area-Efficient 5-Bit Storage
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Solution Overview
Problem
Semiconductor devices face challenges in balancing fast data processing speed with the need for power conservation, particularly in nonvolatile memory devices, and there is a need to efficiently store multi-bit data in reduced areas while minimizing the number of memory cells.
Innovation Solution
A semiconductor device is designed with a page buffer comprising specific latches to store 4-bit original data and a control circuit that determines a program inhibition pattern to invert data based on stored data, allowing efficient encoding and decoding of 5-bit data across two memory cells, reducing the number of latches required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multi-bit data is stored in two memory cells to increase storage capacity, then area efficiency is improved, but the complexity of encoding and data management increases
Solution Approach 1:
The 5-bit data is segmented into two groups: 3 bits stored in the first memory cell and 2 bits stored in the second memory cell. This segmentation allows efficient use of multi-cell storage while managing complexity through structured data distribution across cells
Solution Approach 2:
The patent applies parameter changes by inverting specific data bits based on a program inhibition pattern. The control circuit dynamically changes data parameters (bit inversion) to optimize storage efficiency and manage the complexity of multi-bit storage across two cells
2Area of stationary object
If the number of latches is reduced to improve area efficiency, then area efficiency is improved, but the capability to perform encoding operations may be compromised
Solution Approach 1:
The control circuit is designed with multi-functionality, performing both encoding operations and program inhibition control using the same hardware resources. This allows the system to maintain full encoding capability while using a reduced number of latches, as the control circuit compensates for the reduced latch functionality
Solution Approach 2:
The control circuit acts as an intermediary that manages the interaction between the reduced latch structure and the encoding requirements. It mediates the encoding process by determining program inhibition patterns based on latch data and controlling the inversion operations, thereby maintaining encoding capability despite fewer latches
Data Source
AI summary
A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.