3D NAND Programming With Variable ISPP Pulses to Reduce Programming Time
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Solution Overview
Problem
Memory cells in 3D NAND systems experience adverse voltage coupling effects and initial threshold voltage shifts during programming, leading to inefficiencies and increased programming times due to multi-stage operations.
Innovation Solution
Implementing incremental step pulse programming (ISPP) with variable step pulses for both coarse and fine programming, adjusting pulse sizes based on target programming states to efficiently reach required voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-stage programming operations are used to improve programming accuracy, then the threshold voltage accuracy is improved, but the programming time increases
Solution Approach 1:
The patent segments the programming process into multiple stages (coarse programming followed by fine programming), where each stage uses different verification voltages and programming parameters. This segmentation allows the system to achieve high accuracy by dividing the complex programming task into manageable steps, with coarse programming establishing a baseline and fine programming refining the threshold voltage to precise target levels.
Solution Approach 2:
The patent implements periodic verification and adjustment cycles during programming, where the memory device alternates between applying programming voltages and verifying threshold voltage levels. This periodic action continues through multiple stages until the desired accuracy is achieved, allowing systematic refinement of the threshold voltage while managing overall programming time through optimized cycle structures.
2Manufacturing precision
If multiple programming rounds are performed to reach target voltage range, then the programming accuracy is improved, but the programming efficiency decreases
Solution Approach 1:
The patent dynamically adjusts programming parameters including verification voltages, programming voltages, and pulse widths based on the current programming stage and observed threshold voltage levels. This dynamic adaptation allows the system to optimize each programming round, reducing unnecessary iterations while maintaining high accuracy. The verification voltages are specifically adjusted between coarse and fine programming stages to match the precision requirements of each phase.
Solution Approach 2:
The patent changes multiple parameters across programming stages, including verification voltage levels (lower in coarse programming, higher in fine programming), programming voltage magnitudes, and pulse widths. These parameter changes enable the system to efficiently progress from rough threshold voltage establishment to precise target voltage achievement, improving both accuracy and efficiency by matching parameters to stage-specific requirements.
3Measurement precision
If verification is performed after each programming voltage application, then the threshold voltage control is improved, but the operation time increases
Solution Approach 1:
The patent segments verification operations into stage-specific verification processes, where coarse programming uses lower verification voltages and fewer verification points, while fine programming uses higher verification voltages and more precise verification levels. This segmentation reduces total verification time while maintaining control accuracy by matching verification intensity to the precision requirements of each programming stage.
Solution Approach 2:
The patent performs preliminary coarse programming and verification to establish a baseline threshold voltage range before proceeding to fine programming. This preliminary action narrows the target range for subsequent fine programming, reducing the number of verification iterations needed in later stages and thereby reducing total operation time while maintaining precise threshold voltage control.
Data Source
AI summary
In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first coarse programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second coarse programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.