Hierarchical ROM Encoding for Reduced Die-Space Address Fault Detection
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Solution Overview
Problem
Existing memory systems require significant die space for address fault detection due to the use of extensive ROM encoders, which complicates efficient address fault identification.
Innovation Solution
A hierarchical ROM encoding system with multiple levels of encoders is employed to detect address faults, reducing the number of components and die space required by optimizing the encoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ROM encoders are used for address fault detection, then address fault detection capability is achieved, but die space and component count increase significantly
Solution Approach 1:
The address fault detection function is segmented into two parts: a first ROM encoder that encodes the entire address, and a second ROM encoder that encodes only a portion of the address. This segmentation allows the system to maintain full address fault detection capability while reducing the overall encoding complexity and die space requirements by dividing the encoding task across two specialized encoders rather than using a single large encoder.
2Reliability
If extensive ROM encoders are used for address fault detection, then address fault detection accuracy is maintained, but device complexity increases
Solution Approach 1:
The encoding function is segmented between two ROM encoders with different scopes. The first ROM encoder handles the complete address space, while the second ROM encoder handles only a subset of address lines. This segmentation reduces the complexity of each individual encoder, making the overall system easier to implement and maintain while preserving detection accuracy through the combined output of both encoders.
Solution Approach 2:
The first ROM encoder serves multiple functions: it provides address encoding for fault detection and also generates output that can be used by the second ROM encoder. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity while maintaining comprehensive address fault detection capability.
Data Source
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AI summary
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.