Non-Volatile Memory Read Current Control Using Data State Grouping
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Solution Overview
Problem
Existing non-volatile memory devices face high power consumption during sensing operations due to massively parallel read and program processes, necessitating a need for high-performance and high-capacity memory apparatuses with reduced power consumption.
Innovation Solution
The memory apparatus includes memory cells connected to word and bit lines, with a control mechanism that applies a bit line voltage to determine threshold voltages and groups cells into data state groups, followed by supplying near-zero voltage to bit lines during subsequent read operations, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If massively parallel sensing is used to improve read and program performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent segments the sensing operation into multiple passes, where each pass reads a specific subset of data states. In the first pass, only odd data states (1, 3, 5, 7) are read, and in the second pass, only even data states (0, 2, 4, 6) are read. This segmentation reduces the number of conducting memory cells active simultaneously during each sensing operation, thereby reducing power consumption while maintaining overall read performance.
Solution Approach 2:
The patent applies partial action by selectively enabling only the necessary bit lines for the current data state group being read. Instead of activating all bit lines for all data states simultaneously, the system activates bit lines only for the specific data states required in the current pass. This partial activation significantly reduces the total current draw during sensing operations.
2Measurement precision
If multiple sensing passes are used to resolve all memory states, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary action by reading odd data states in the first pass and using that information to lock out those cells in the second pass. This preliminary reading and locking out strategy allows the second pass to focus only on even data states, eliminating redundant sensing operations and reducing the total time required to read all memory states while maintaining precise state resolution.
Solution Approach 2:
The patent uses feedback from the first sensing pass to control the second pass. The results from reading odd data states in the first pass are used to determine which bit lines should be locked out during the second pass. This feedback mechanism ensures that each pass reads only the necessary data states, optimizing both precision and speed by avoiding redundant operations.
3Productivity
If all bit lines are activated during reading, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent applies local quality by differentiating the voltage supply to different bit lines based on the data state groups being read. Bit lines associated with currently active data state groups receive appropriate voltages for sensing, while bit lines associated with locked-out data state groups receive near-zero voltage. This localized voltage control maintains parallel read capability for active cells while minimizing energy consumption by inactive bit lines.
Solution Approach 2:
The patent implements partial action by activating only the subset of bit lines necessary for the current sensing pass. Instead of maintaining full voltage on all bit lines throughout the read operation, the system dynamically activates bit lines only when their associated data states need to be read, significantly reducing total current consumption while preserving parallel read performance for the active subset.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells retain a threshold voltage corresponding to data states. A control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. The control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. The control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.