Semiconductor Memory With Dual-Gate Floating-Body Noise Control
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face issues with capacitive coupling between the word line and the floating body, leading to noise interference and difficulties in maintaining a sufficient potential difference between storage states, causing erroneous reading and rewriting.
Innovation Solution
A semiconductor memory device with multiple pages of memory cells, each comprising a semiconductor body, impurity regions, and gate conductor layers, where voltages are controlled to retain and discharge positive holes generated by impact ionization, utilizing capacitive couplings to stabilize the floating body voltage during write and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body increases causing reading errors
Solution Approach 1:
The gate conductor layer is divided into two separate layers: a first gate conductor layer and a second gate conductor layer. This segmentation allows independent control of voltages applied to each gate layer, enabling differential voltage control schemes that can suppress capacitive coupling noise while maintaining high integration density.
Solution Approach 2:
A plate line is introduced as an intermediary element between the word line and the memory cell structure. The plate line acts as a shielding element that reduces direct capacitive coupling between the word line and the floating body, thereby decreasing noise interference while preserving the capacitor-less device structure.
2Speed
If strong capacitive coupling is used for fast write operation, then write speed is improved, but noise interference increases causing erroneous data retention
Solution Approach 1:
The voltage applied to the first and second gate conductor layers is made dynamic and controllable. During write operations, different voltage combinations can be applied to the two gate layers to optimize both write speed and data retention. The system can switch between different voltage states (e.g., both high, one high one low, both low) depending on the operational phase.
Solution Approach 2:
The invention changes the electrical parameters by applying different voltages to the two gate conductor layers. By controlling the voltage difference between the first and second gate layers, the system can modulate the electric field distribution to achieve fast charge injection during write while preventing excessive noise during data retention phases.
3Device complexity
If single gate conductor layer is used, then device structure is simplified, but noise suppression capability is insufficient
Solution Approach 1:
The gate conductor layer is segmented into two distinct layers that can be independently controlled. This segmentation transforms a single uncontrollable gate into two controllable gates, enabling noise suppression through differential voltage control while maintaining relatively simple device fabrication processes.
Solution Approach 2:
The gate structure uses a composite configuration with two gate conductor layers separated by an insulating layer. This composite structure provides both the simplicity of a planar device layout and the noise suppression capabilities of a shielded configuration, effectively reducing capacitive coupling noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable storage states with reduced noise interference, enabling reliable data retention and improved read/write margins, facilitating the commercial viability of capacitor-less DRAMs.
Implementation Method 1
a group of positive holes generated by an impact ionization phenomenon or a gate-induced drain leakage current are retained inside the semiconductor body
Implementation Method 2
with one or both of first capacitive coupling between the first gate conductor layer and the semiconductor body and second capacitive coupling between the second gate conductor layer and the semiconductor body
Implementation Method 3
a group of positive holes generated by an impact ionization phenomenon or a gate-induced drain leakage current are retained inside the semiconductor body
Data Source
AI summary
A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from among the pages and the page erase operation is performed.