Semiconductor Storage Bit-Line Voltage Control for Read Consistency
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Solution Overview
Problem
Existing semiconductor storage devices face performance issues in read and write operations due to varying write speeds and threshold voltage differences among memory cells, particularly those near and far from structural features like slits, leading to inconsistent operation characteristics.
Innovation Solution
The semiconductor storage device employs a control circuit to apply different voltages to bit lines based on the memory cell's proximity to structural features, ensuring consistent read and write operations by adjusting voltages and sense times to match the characteristics of memory cells near and far from slits, thereby equalizing threshold voltages and speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single voltage is applied to all bit lines during read operations, then the device structure remains simple, but memory cells near and far from slits exhibit different read speeds and threshold voltages, leading to inconsistent operation characteristics
Solution Approach 1:
The patent applies different voltages to different bit lines based on the spatial location of memory cells relative to slits. Specifically, a first voltage is applied to bit lines connected to memory cells near slits, while a second voltage is applied to bit lines connected to memory cells far from slits. This local differentiation compensates for the varying threshold voltages and read speeds caused by the slit structure, ensuring consistent operation characteristics across all memory cells.
2Measurement precision
If different voltages are applied to bit lines based on memory cell location, then read and write operation accuracy improves, but the control circuit complexity increases
Solution Approach 1:
The control circuit is designed to selectively apply different voltages to different bit lines based on the spatial relationship between memory cells and slits. The circuit includes voltage selection logic that determines which voltage to apply based on the bit line's position, thereby improving read and write accuracy while managing control complexity through systematic voltage distribution.
Solution Approach 2:
The patent changes the voltage parameter applied to bit lines based on the location of memory cells. By adjusting the voltage level according to spatial position (near or far from slits), the system compensates for physical variations in threshold voltage and read speed, thereby improving measurement precision without requiring fundamental changes to the memory cell structure.
3Productivity
If uniform voltage is applied during write operations, then the write process is simple, but memory cells near and far from slits experience different write speeds, reducing overall productivity
Solution Approach 1:
During write operations, the control circuit applies different voltages to bit lines depending on whether the target memory cells are near or far from slits. This local differentiation ensures that all memory cells reach the required threshold voltage at similar rates, equalizing write speeds across the array and improving overall write productivity without requiring complex per-cell control.
Data Source
AI summary
A semiconductor storage device includes a first word line, a first insulating layer extending along the first word line, a first memory cell connected to the first word line, a second memory cell connected to the first word line, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a control circuit. The second memory cell is farther from the first insulating layer than the first memory cell. The control circuit is configured to apply a first voltage to the first bit line during a read operation of the first memory cell, and apply a second voltage to the second bit line during a read operation of the second memory cell. The second voltage is higher than the first voltage.