Memory Device Data Strobe Phase Division for High-Speed, Low-Power Transfer
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Solution Overview
Problem
Existing memory devices face challenges in transmitting data at high speed while minimizing power consumption, as high-frequency data strobe signals increase power consumption.
Innovation Solution
The memory device employs a buffer die with a control logic circuit that generates internal write data strobe signals with different phases, initializing them to given values before the write data strobe signal toggles, allowing data transmission and reception without separate auto-synchronization, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data strobe signal frequency is increased to enable high-speed data transmission, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by initializing the internal write data strobe signals to given values before the write data strobe signal starts to toggle. The control logic circuit generates a reset signal that pre-initializes the internal strobe signals, eliminating the need for separate auto-synchronization operations during data transmission, thereby reducing power consumption while maintaining high-speed transmission capability
Solution Approach 2:
The patent extracts and eliminates the separate auto-synchronization circuit and operation from the data transmission system. By initializing the internal write data strobe signals beforehand and using the toggling write data strobe signal directly to generate phase-divided internal strobe signals, the patent removes the redundant synchronization mechanism that would otherwise consume additional power
2Reliability
If separate auto-synchronization circuits are added to maintain signal synchronization, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent merges the synchronization function into the existing write data strobe signal path. The internal write data strobe signals are generated by dividing the frequency of the toggling write data strobe signal, combining the synchronization and clocking functions into a unified mechanism that eliminates separate synchronization circuits
Solution Approach 2:
The patent implements self-service by enabling the internal write data strobe signals to self-initialize through the reset signal generated from the write command detection. The system automatically synchronizes itself using the inherent toggling of the write data strobe signal without requiring external or separate synchronization control circuits
Data Source
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AI summary
Disclosed is a memory device that includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.