Memory Device Read Reliability with Staged Bit-Line Precharge
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Solution Overview
Problem
As the degree of integration of memory devices increases, electrical influences between adjacent elements increase, leading to deteriorated reliability in program, read, and erase operations.
Innovation Solution
A memory device with a peripheral circuit that includes page buffers to increase the channel voltage of strings by applying a first precharge voltage during the set-up phase, a second precharge voltage lower than the first during the read phase, and discharges the bit lines in the discharge phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of the memory device is increased, then the capacity and weight reduction are improved, but the electrical influence between adjacent elements increases leading to deteriorated reliability
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a first precharge voltage before the actual read operation. This preliminary voltage application prepares the channel voltage in advance, ensuring that even with high integration density causing electrical interference, the channel maintains sufficient voltage level for reliable read operations. The precharge phase occurs before the read phase, proactively compensating for the deteriorated electrical conditions.
2Area of stationary object
If the degree of integration is increased, then the device size is reduced, but the electrical influence between adjacent elements increases
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the bit line voltage through two distinct precharge voltage levels. The first precharge voltage (higher) is applied during the set-up phase to establish adequate channel voltage, and the second precharge voltage (lower) is applied during the read phase. This parameter adjustment compensates for the increased electrical influence between closely spaced elements, maintaining reliable operation despite reduced device area.
3Device complexity
If a single precharge voltage is applied to bit lines, then the device operation is simplified, but the channel voltage cannot be optimized leading to reduced read operation reliability
Solution Approach 1:
The patent applies segmentation by dividing the precharge operation into two distinct phases with different voltage levels. The first precharge voltage is applied during the set-up phase to boost channel voltage, and the second precharge voltage is applied during the read phase. This segmentation allows optimization of channel voltage for reliable read operations while maintaining manageable device complexity through structured control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of read operations by maintaining optimal channel voltages and preventing voltage fluctuations, thereby improving overall device performance.
Implementation Method 1
apply a first precharge voltage to the bit lines in a set-up phase of the read operation
Implementation Method 2
apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation
Implementation Method 3
discharge the bit lines in a discharge phase of the read operation
Data Source
AI summary
A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.