3D Memory Wrapped Word Lines for Leakage Isolation
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Solution Overview
Problem
Existing 3D memory devices suffer from leakage current issues due to shared semiconductor channels that extend across multiple word lines, degrading performance and reading window efficiency.
Innovation Solution
The 3D memory device design includes memory cells with semiconductor channels that are closed-ended and wrap around respective access lines, isolating neighboring memory levels and confining electrical fields within the channel, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared semiconductor channels extend across multiple word lines, then device complexity is reduced and manufacturing is simplified, but leakage current increases and performance degrades
Solution Approach 1:
The patent segments the continuous semiconductor channel into isolated sections by introducing air gaps at each memory level. These air gaps divide the originally shared channel into discrete segments, preventing electrical leakage between adjacent memory levels while maintaining the vertical stacking architecture. This segmentation resolves the contradiction by allowing channel isolation without requiring complete separate channel structures for each memory cell.
2Ease of manufacture
If shared semiconductor channels are used across multiple word lines, then manufacturing process is simplified, but gate controllability is reduced
Solution Approach 1:
By introducing air gaps that segment the channel at each memory level, the patent enables independent gate control for each memory cell. The air gaps electrically isolate the channel sections, allowing each word line to control its corresponding memory cell without interference from adjacent levels, thereby improving gate controllability while maintaining a relatively simple manufacturing process.
Solution Approach 2:
The air gaps act as intermediary insulating structures between adjacent memory levels. These gaps serve as mediators that prevent electrical interaction between channels at different levels, enabling independent gate control while requiring minimal modification to the manufacturing process. The air gaps are formed through selective removal of sacrificial materials, adding little complexity to fabrication.
3Device complexity
If continuous channels extend across multiple levels, then device structure is simplified, but reading window efficiency is degraded
Solution Approach 1:
The patent introduces air gaps that segment the continuous channel into discrete isolated sections at each memory level. This segmentation prevents electrical interference and leakage between adjacent memory levels, thereby improving reading window efficiency. The segmented channel structure maintains vertical stacking simplicity while enabling precise detection and reading operations by eliminating cross-level electrical interactions.
Data Source
AI summary
A memory device includes a first memory cell. The first memory cell includes: a first conductor structure extending along a lateral direction; a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; and a first semiconductor film wrapping around the first portion of the first memory film. A second conductor structure extends along a vertical direction and is coupled to a first end portion of the first semiconductor film along the lateral direction. A third conductor structure extends along the vertical direction and is coupled to a second end portion of the first semiconductor film along the lateral direction.