Semiconductor Memory Threshold Combinations for Three-Bit Storage
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Solution Overview
Problem
Existing NAND-type flash memories face challenges in efficiently storing multiple bits per memory cell due to limitations in threshold voltage settings, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
The semiconductor memory system employs two memory cell arrays with distinct threshold voltage settings, allowing for the storage of three bits by combining the threshold voltages of memory cells within each array, thereby enhancing data storage capacity and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional NAND-type flash memory with single threshold voltage setting is used, then device structure is simple, but data storage capacity per cell is limited to 1 bit
Solution Approach 1:
The memory cell array is divided into two distinct arrays: first memory cell array with first threshold voltage setting and second memory cell array with second threshold voltage setting. This segmentation allows each array to store different bit values, enabling multi-bit storage per cell while maintaining manageable complexity through modular organization
Solution Approach 2:
The invention adds a new dimension to traditional flash memory by introducing a second threshold voltage setting dimension. Instead of only varying charge trap states (single dimension), the system now utilizes two independent threshold voltage dimensions (first and second), allowing 3-bit storage through the combination of threshold voltage levels and charge trap states
2Quantity of substance
If multiple threshold voltage settings are implemented to store 3 bits per cell, then data storage density increases, but read and write operation complexity increases
Solution Approach 1:
Write operations are segmented into distinct phases for first and second memory cell arrays, allowing independent programming of different bit values. Read operations are similarly segmented, with separate read paths for each array, enabling parallel processing and reducing overall operation complexity despite multi-bit storage
Solution Approach 2:
Charge trap states serve as an intermediary mechanism that works in conjunction with threshold voltage settings. This intermediary allows the system to encode additional bit information without requiring complete redesign of the read/write circuits, as the charge trap states can be independently controlled and read
3Adaptability or versatility
If two memory cell arrays with different threshold voltages are used, then bits can be stored by combining threshold voltages, but device structure becomes more complex
Solution Approach 1:
Both first and second memory cell arrays use the same basic memory cell structure and are controlled by the same control circuitry, but they serve different functions by having different threshold voltage settings. This multi-functionality allows the system to store multiple bits using identical hardware components, reducing overall device complexity
Solution Approach 2:
The invention changes the threshold voltage parameter of memory cells to create two distinct arrays with different electrical characteristics. By adjusting this fundamental parameter, the system achieves enhanced data encoding capability without modifying the physical structure or material composition of the memory cells
Data Source
AI summary
According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.