Resistance-Variable Memory Cell Pairing for Lower Bipolar Sense Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing resistance variable memory cells consume excessive power during bipolar sense operations due to certain data state combinations causing both cells to switch states, leading to inefficient power consumption.
Innovation Solution
Implementing a programming scheme where two specific data state combinations in pairs of memory cells are ineligible to store a single data value, reducing power consumption by limiting double switching during sense operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional bipolar sense operations are performed on memory cells, then data can be read from the cells, but power consumption increases due to both cells switching states
Solution Approach 1:
The patent applies preliminary action by pre-defining ineligible data state combinations before sense operations are performed. By establishing which combinations of first and second memory cell states are ineligible to represent a single data value, the system prevents double switching during sense operations, thereby reducing power consumption while maintaining data reading capability
Solution Approach 2:
The patent changes the parameter space of valid data state combinations by eliminating two specific ineligible combinations from the total possible states. This parameter change restricts the state space such that certain combinations of memory cell states cannot occur, thereby preventing the harmful double switching effect during bipolar sense operations
2Adaptability or versatility
If all possible data state combinations are allowed in memory cells, then storage flexibility is maximized, but power consumption increases due to double switching
Solution Approach 1:
The patent modifies the parameter space of valid data states by changing which combinations are eligible. Specifically, it identifies and eliminates two ineligible combinations (where both cells are in state 0 or both are in state 1) from the total possible state space, thereby reducing power consumption while maintaining sufficient storage flexibility through the remaining seven valid combinations
Solution Approach 2:
The patent converts the potential harm of having all state combinations available (which causes double switching and power loss) into a benefit by strategically eliminating specific combinations. The ineligible state combinations that would cause harmful double switching are precisely the ones removed, transforming the state space constraint into a power-saving mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption by approximately 15% compared to traditional methods by minimizing power consumption during bipolar sense operations.
Implementation Method 1
resistance variable memory cells that can store data based on the resistance state of a storage element (e.g., a memory element having a variable resistance)
Implementation Method 2
programmed to a target data state (e.g., corresponding to a particular resistance state) by applying sources of an electrical field or energy, such as positive or negative electrical pulses
Implementation Method 3
A state of a resistance variable memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage
Data Source
AI summary
Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.